Hewlett-packard Development Company, L.P.

Intel Corporation

Thomas Justin Sullivan

Glenn T Colon-Bonet

Samuel D Naffziger

Barry Joseph Arnold

Stephen L Bass

Lei Wang

Randall J Nettleton

Systems, methods, and other embodiments associated with time separated signals are described. One system embodiment includes a delay circuit, two or more sets of interconnects, and a clocked deracer circuit. In the system embodiment, at least one of the sets of interconnects is arranged as a shield for another set of interconnects. In the system embodiment, the delay circuit may select a timing delay to apply to the first signal to produce the near-end signal based, at least in part, on a desired ratio between a reduction in the slack associated with a setup time on a far-end receiver and a reduction in the slack associated with a hold time on a near-end receiver.

Time separated signals

An apparatus and method for performing single-instruction multiple-data instructions using a single multiply-accumulate unit while minimizing operational latency. The multiply-accumulate unit generates a first half and a second half of a data result. A register stores the first half of the data result. A miscellaneous-logic unit determines when to release the first half of the data result from the register to synchronize the first half and the second half of the data result.

Apparatus and method for performing single-instruction multiple-data instructions

The present invention generally relates to an apparatus and method for efficiently summing the partial product bits produced by a multiplier. Briefly described, in architecture, the apparatus includes a first array of odd/even summation circuitry, a second array of odd/even summation circuitry, and a linear array of adders. The apparatus is configured to add a row of partial product bits produced by a multiplier in multiplying a first operand with a second operand. The first array of odd/even summation circuitry produces a first summation of a portion of the partial product bits. The second array of odd/even circuitry produces a second summation of the other partial product bits. The linear array of adders then adds the first summation and the second summation to produce a carry save representation of a product bit (i.e., a bit of the product produced by multiplying the first operand by the second operand).

Apparatus and method for increasing performance of multipliers utilizing regular summation circuitry

Circuitry for scanning and observing domino CMOS logic or other logic gates. Master and slave stages includes circuitry for latching a bit into the master stage through pulsing of a clock signal and subsequently latching the bit into the slave stage through pulsing of another clock signal. The number of transistors required for scanning is minimized by using existing latch structures within the logic.

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Fort Collins, CO, United States of America

Thomas Justin Sullivan