Agere Systems Inc.

Zarlink Semiconductor Limited

Agere Systems Guardian Corp.

Other

Lucent Technologies Inc.

Microsemi Semiconductor (u.s.) Inc.

Thomas Joseph Krutsick

Bailey R Jones

John Charles Desko

Brian Eric Thompson

Chung-Ming Hsieh

John Joseph Bastek

Steven W Wallace

Michael J Evans

Robert D Plummer

Tzu-Yen Hsieh

Steve Wallace

John Michael Siket, Jr

Christopher James Speyer

The present invention provides embodiments of a musical instrument preamplifier. It is especially suited to acoustic and electric guitars and basses. All components, including the power source, are contained within or on the body of the instrument. The preamplifier dubbed BPTD (for Battery Powered Tube Driver) contains a vacuum tube input stage and may utilize a second stage consisting of either a vacuum tube or semiconductor device, such as a JFET. Circuitry is included to bias the cathode heater and the preamplifier circuit with no dangerous high voltages present. The tube may be mounted on the instrument body to provide for a pleasing display.

Musical instrument preamplifier

The present invention provides embodiments of a capacitor and a method of forming the capacitor. The capacitor includes one or more trenches formed in a semiconductor layer above a substrate. The trench includes dielectric material deposited on the trench walls and a conductive fill material formed within the trench and above the dielectric material. The capacitor also includes one or more first doped regions formed adjacent the trench(es) in the semiconductor layer. The first doped region is doped with a first type of dopant. The capacitor further includes one or more second doped regions formed adjacent the first doped region(s) in the semiconductor layer. The second doped regions are doped with a second type of dopant that is opposite to the first type of dopant.

Trench capacitor for high voltage processes and method of manufacturing the same

The present invention provides a method of forming a bipolar transistor. The method includes doping a silicon layer with a first type of dopant and performing a first implant process to implant dopant of a second type opposite the first type in the silicon layer. The implanted dopant has a first dopant profile in the silicon layer. The method also includes performing a second implant process to implant additional dopant of the second type in the silicon layer. The additional implanted dopant has a second dopant profile in the silicon layer different than the first dopant profile. The method further includes growing an insulating layer formed over the silicon layer by consuming a portion of the silicon layer and the first type of dopant.

Methods of counter-doping collector regions in bipolar transistors

The present invention provides a method of forming an optically triggered switch. Embodiments of the method include forming a silicon layer, forming one or more trenches in the silicon layer, and forming one or more silicon diodes in the silicon layer. Embodiments of the method also include forming a first thyristor in the silicon layer such that the first thyristor is physically and electrically isolated from the silicon diode(s) by the trench(es). The first thyristor is configured to turn on in response to electromagnetic radiation generated by the silicon diode(s).

Method of forming a light activated silicon controlled switch

The present invention provides an optically triggered switch and a method of forming the optically triggered switch. The optically triggered switch includes a silicon layer having at least one trench formed therein and at least one silicon diode formed in the silicon layer. The switch also includes a first thyristor formed in the silicon layer. The first thyristor is physically and electrically isolated from the silicon diode by the trench and the first thyristor is configured to turn on in response to electromagnetic radiation generated by the silicon diode.

Light activated silicon controlled switch

The present invention provides a method and apparatus for providing electro-static discharge (ESD) protection between a first and a second circuit node. One embodiment of the ESD protection circuit includes one or more steering diodes that generate electromagnetic radiation and couple the first circuit node to ground in response to a voltage applied to the first circuit node. The ESD protection circuit also includes a latch circuit that couples the first circuit node to ground in response to the electromagnetic radiation generated by the steering diode(s).

Optically triggered electro-static discharge protection circuit

The present invention provides an optical isolator and a method of forming the optical isolator. Embodiments of the optical isolator include a silicon layer having at least one trench formed therein. The trench has a resistance that varies in response to electromagnetic radiation. Embodiments of the optical isolator also include at least one first diode formed in the silicon layer such that the trench encompasses the first diode. The first diode is configured to generate electromagnetic radiation in response to an applied signal. Embodiments of the optical isolator further include first and second regions formed in contact with the trench such that the resistance between the first and second contact regions varies in response to the electromagnetic radiation generated by the first diode.

Integrated silicon optical isolator

An integrated circuit includes a field plated resistor having enhanced area thereover for routing metal conductors, formed in the same layer of metal as forms contacts to the resistor, is fabricated by a sequence of processing steps. A resistor having a resistor body and a contact region at each end thereof is formed in an active region of a semiconductor substrate. A first layer of insulative material is formed over the resistor and a window is created through the first layer of insulative material to the resistor body to form a first contact region. A layer of polysilicon is formed over the first insulative layer to define a field plate, the polysilicon field plate being contiguous with the first contact region of the resistor and extending over the resistor body to substantially to the other contact region, as layout, design, and fabrication rules permit. A second insulative layer is formed over the polysilicon layer. Windows are created in the second insulative layer to provide access to the polysilicon field plate and the second contact region. A metal layer is applied and unwanted metal is etched away to provide conductors over the polysilicon field plate of a field plated resistor having enhanced area thereover for routing metal conductors formed in the same layer of metal as forms contacts to the resistor.

Field plated resistor with enhanced routing area thereover

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the same. In one advantageous embodiment, the semiconductor device includes a doped layer located over a semiconductor substrate, and an isolation trench located in the doped layer and having a dielectric layer located on a sidewall thereof. The semiconductor device may further include a conductive material located within the isolation trench and an interconnect that electrically connects the conductive material and the doped layer.

Semiconductor device having an interconnect that electrically connects a conductive material and a doped layer, and a method of manufacture therefor

A Schottky diode is fabricated by a sequence of fabrication by a sequence of fabrication steps. An active region of a semiconductor substrate is defined in which a Schottky diode is fabricated. At least first and second layers of insulating material are applied over the active area. A first layer of insulating material, having a first etching rate, is applied over the active area. A second layer of insulating material having a second, greater, etch rate is applied over the first layer of insulating material to a thickness that is about twice the thickness of the first layer of insulating material. The insulating material is patterned and a window is etched through the layers of insulating material to the semiconductor substrate. Metal is applied and unwanted metal is etched away leaving metal in the window forming a Schottky contact therein. One or more barrier layers may be employed.

Field plated schottky diode and method of fabrication therefor

Complementary bipolar transistors are fabricated on a semiconductor wafer by forming, first and second electrodes corresponding to first and second complementary transistors, respectively. A first impurity is selectively introduced into the first and second electrodes. A third electrode corresponding to the first transistor is formed, the third electrode being self-aligned with and electrically isolated from the first electrode, and a fourth electrode is formed corresponding to the second transistor, the fourth electrode being self-aligned with and electrically isolated from the second electrode. A second impurity is selectively introduced into the third and fourth electrodes. First active regions of the first and second transistors are formed, whereby the first impurity diffuses into the first active regions. Likewise, second active regions of the first and second transistors are formed, whereby the second impurity diffuses into the second active regions. A reduction in the number of fabrication steps and/or masks is thereby achieved.

Method of fabricating complementary self-aligned bipolar transistors

The present invention provides a semiconductor device, a method of manufacture therefor, and an integrated circuit including the semiconductor device. The semiconductor device may include a well doped with a P-type dopant located over a semiconductor substrate. The semiconductor device may further include a buried layer including the P-type dopant located between the well and the semiconductor substrate, and a gate located over the well.

Semiconductor device having a buried layer for reducing latchup and a method of manufacture therefor

Integrated circuit devices are formed in a substrate wafer using selective epitaxial growth (SEG). Non-uniform epitaxial wafer thickness results when the distribution of SEG regions across the surface of the wafer is non-uniform, resulting in loading effects during the growth process. Loading effects are minimized according to the invention by adding passive SEG regions thereby giving a relatively even distribution of SEG growth regions on the wafer. The passive regions remain unprocessed in the finished IC device.

Integrated circuit device substrates with selective epitaxial growth thickness compensation

Field plated Schottky diode

The present invention provides a bipolar transistor having a collector located in a semiconductor substrate having a given bandgap, and a base in contact with the collector. The base has a bandgap less than the bandgap of the substrate. In addition, the bipolar transistor further includes an emitter located over the base, where the emitter has a bandgap greater than the bandgap of the substrate. A method of forming a bipolar transistor, and an integrated circuit incorporating the bipolar transistor or the method, are also disclosed.

Growing community of inventors

Fleetwood, PA, United States of America

Thomas Joseph Krutsick