Intermec IP Corporation

Hand Held Products, Inc.

Intermec, Inc.

Thomas John Schuster

Ronald L Mahany

Daniel E Alt

Michael K Ellis

Robert Arlan Kohtz

Mark Howe

John Jorgenson

Fengyu Ge

A mobile device has one or more sensors that are configured to detect the presence of fog or frost on a surface of the mobile device. A battery provides power to the mobile device. An energy transfer element, when activated, removes fog or frost from a surface of the mobile device. A programmed processor, within the mobile device, is programmed to: read one or more sensors disposed in the mobile device to determine if there is a fog or frost condition; upon detecting a fog or frost condition, activating the energy transfer element to remove fog or frost; and upon detecting an absence of the fog or frost condition, deactivating the heater energy transfer element.

Managing energy usage in mobile devices

A device includes a switch having multiple ports, an antenna coupled to each corresponding port, a tunable matching network coupled between each antenna and each port, and a controller to detune ports having antennas that are not transferring power when a selected antenna is transferring power.

RFID reader antenna port isolation

In an exemplary embodiment, a multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. A direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output. A multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. A multi-rate digital data filter receives the converted digital data and produces a filtered digital output. An output scaler receives the filtered digital output and produces a scaled and filtered digital output. Finally, an adder combines the scaled and filtered digital output with a center frequency input and produces the converted output.

Multiple date rate filtered modulation system for digital data

A multi-rate data modulation circuit includes a multi-rate data conversion circuit and a modulator such as a direct digital synthesis circuit. The multi-rate data conversion circuit receives digital data at varying data rates, receives a data rate input corresponding to the digital data and converts the digital data to a converted output based upon the data rate input. The direct digital synthesis circuit receives the converted output and synthesizes a modulated output signal based upon the converted output. The multi-rate data conversion circuit may include a multi-rate converter, a multi-rate digital data filter, an output scaler and an adder. The multi-rate converter receives the digital data, the data rate input and a clock signal and converts the digital data to converted digital data. The multi-rate digital data filter receives the converted digital data and produces a filtered digital output. The output scaler receives the filtered digital output and produces a scaled and filtered digital output. Finally, the adder combines the scaled and filtered digital output with a center frequency input and produces the converted output. The multi-rate digital data filter may include a look-up table that produces filter parameters based upon the converted digital data and that operates at multiple data rates. The multi-rate digital data filter may include a digital data filter look-up table, a data rate decode circuit and a plurality of multiplexors. In such case, the data rate decode circuit receives the data rate input and produces control signals therefrom. Each of the plurality of multiplexors receives a portion of the converted digital data and control signals from the data rate decode circuit such that the multiplexors selectively provide the converted digital data to the digital data filter look-up table to produce the filtered digital output.

Multiple data rate filtered modulation system for digital data

An integrated circuit includes a demodulator having delay circuitry and demodulation control circuitry that may be fully formed within a common integrated circuit. The delay circuitry receives an input signal and generates a delayed input signal. The demodulation control circuitry generates a demodulated output based upon the input signal and the delayed input signal that has a level that is proportional to, or a finction of, a period of a respective cycle of the input signal. The demodulation control circuitry includes pulse generation circuitry, pulse delay circuitry, pulse conversion circuitry and sampling circuitry. The pulse generation circuitry generates a signal pulse based upon the input signal and the delayed input signal with a duration that is proportional to at least one period of the input signal. The pulse delay circuitry generates a delayed signal pulse based upon the signal pulse. The pulse conversion circuitry generates a converted signal that has a level based upon the duration of the signal pulse. The sampling circuitry samples the converted signal based upon a sample pulse to generate the demodulated output based upon the level of the converted signal. The delay circuitry and pulse delay circuitry each include a plurality of cascaded semiconductive elements that, in combination, produce a desired delay duration.

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Cedar Rapids, IA, United States of America

Thomas John Schuster