Unisys Corporation

Thomas John Adelmeyer

Kenichi Tsuchiya

Michael L Haupt

Lewis A Boone

In a high speed main frame computer system, a high speed instruction processor is provided with a high speed cache memory. The cache memory is provided with a plurality of associated memories including a tag memory. Every time the instruction processor attempts to access the cache memory, a cache set address is generated which accesses the associated memories to provide most recently used (MRU) block information, validity information and degrade block information. The accessed information is applied as inputs to a cache logic system. The cache logic system logically modifies the information to generate an update of the MRU information and writes the modified MRU information into the MRU associated memory at the set address without control or supervision on the part of the instruction processor. The cache logic system also generates the least recently used (LRU) block coded information using the MRU information, validity information and degraded block information for cache block replacement.

Least recently used block replacement for four block cache logic system

A virtual memory computing system is provided with a novel table-look-aside-buffer (TLB). The table-look-aside-buffer is located in cache memory and provides high speed verification that a page address being accessed by the instruction processor is present in the high speed mass storage unit (MSU) of the computer system. In the event of a page miss in the TLB, the control circuits associated with the TLB fetch a page descriptor and generate a translated real page address which is stored in the TLB in an invalidated (decelerated) or non-degraded and least recently used address.

Hit enhancement circuit for page-table-look-aside-buffer

A method of and apparatus for efficiently transferring data between a memory system and an instruction processor having a dedicated cache memory. A read request within the instruction processor for a data element not currently stored within the dedicated cache memory creates a read cache miss condition. A transfer of the eight word block containing the requested data element is initiated from the memory system beginning with the 72 bit double word containing the requested data element. The eight word block of data is placed into a block buffer upon being received by the instruction processor. The instruction processor is permitted to resume instruction execution and access to the cache memory as soon as the requested data element has been received by the block buffer. The eight word data block is transferred from the block buffer to cache memory at the next read cache miss condition. The block buffer has a no save designator for block transfers and other accesses for which near term subsequent access to buffered data is unlikely. Data designated no save is not transferred from the block buffer to the cache memory.

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Hillsboro, OR, United States of America

Thomas John Adelmeyer