Freescale Semiconductor,inc.

Motorola Corporation

Nxp Usa, Inc.

Thomas Jew

Richard Eguchi

David W Chrudimsky

Anirban Roy

Frank Kelsey Baker, Jr

Qadeer A Qureshi

Timothy J Strauss

James David Burnett

Ronald J Syzdek

Thomas S Harp

Edward Bryann C Fernandez

Jon Scott Choy

Gowrishankar L Chindalore

Craig T Swift

Clinton C Kuo

Thomas R Toms

James B Eifert

Jack M Higman

Wallace B Harwood, Iii

Juan Buxo

Peter J Kuhn

Danny P Shum

Sushama Davar

Cheri L Harrington

Botang Shao

Robert Wayne Sparks

Larry J Grieve

Curtis F Wyman

Richard Kazuki Eguchi

Yongliang Wang

Kishna Weaver

A memory includes a row decoder that receives an address of a row to be read and an operand. The memory includes a memory array of bitcells that can be configured to store N-bit weight values in which N is an integer greater than one. The row decoder is configured to, for a multiplication mode read operation at the selected word line, selectively activate the selected word line based on a bit value of the received operand to selectively read an N-bit weight value based on a bit value of the operand. Such an operation may in some embodiments, perform a multiplication operation of the bit value of the operand and the N-bit weight value.

Memory reads of weight values

A method and apparatus for generating an address sequence in a memory device is provided. The method includes providing a memory array having a set of unique addresses, storing one of a first subset of the set of unique addresses in a first storage element, storing one of a second subset of the set of unique addresses in a second storage element, and generating a sequence of addresses to test the memory array. The sequence of addresses are formed by alternately outputting addresses stored in the first storage element and the second storage element such that the sequence of addresses causes each unique address of the set to transition only once. The sequence of addresses can be used to efficiently test the memory array during a built-in self-test (BIST).

Full address coverage during memory array built-in self-test with minimum transitions

A method uses a memory that includes a plurality of non-volatile memory (NVM) cells; a plurality of word lines; a plurality of bit lines; and an amplifier having an inverting input, a non-inverting input, and an output; and a capacitance coupled to the inverting input includes. A reference is coupled to the non-inverting input. The output of the amplifier is coupled to the inverting input of the amplifier while the non-inverting input receives the reference. The output is decoupled from the inverting input to store a voltage on the inverting input of the amplifier. A non-volatile (NV) element of a first NVM cell of the plurality of NVM cells is coupled to the non-inverting input. An output signal representative of the state of the NVM cell is provided.

Capacitive sensing and reference voltage scheme for random access memory

Transitioning to all addresses of a memory array during BIST includes arranging the addresses as a matrix with rows of the matrix corresponding one to one to the plurality of addresses of the memory array and columns of the matrix corresponding one to one to the plurality addresses of the memory array. A column of a selected current location can correspond to a destination address of a memory transition. The destination addresses can identify a candidate row of the matrix which corresponds to the destination address. The candidate row can be different from a row of the current location. A next location can be determined that has not been recorded in the candidate row that has a minimum column distance from the column of the first location as compared to other locations that have not been recorded in the candidate row.

Full address coverage during memory array built-in self test with minimum transitions

A non-volatile memory device includes an array of non-volatile memory cells. A memory cell in the array of memory cells includes a first resistive element including a first terminal and a second terminal, a second resistive element including a first terminal and a second terminal, and a select transistor including a gate electrode coupled to a word line, a first current electrode coupled to the first terminal of the first resistive element and the first terminal of the second resistive element, and a second current electrode coupled to a bit line. The second terminal of the first resistive element is coupled to a first source line, and the second terminal of the second resistive element is coupled to a second source line.

Non-volatile random access memory (NVRAM)

An operating voltage and reference current are adjusted in a memory device. At least a portion of an array of memory cells is preconditioned to an erased state using an erase verify voltage on word lines coupled to the memory cells and a first reference current in sense amplifiers coupled to bit lines for the array. A test reference current is set for the sense amplifiers. A bitcell gate voltage is set on the word lines to a present overdrive voltage. The at least a portion of the array is read. If any of the memory cells in the at least a portion of the array are read as being programmed, the present overdrive voltage is increased until none of the memory cells in the at least a portion of the array are read as being programmed.

Non-volatile memory (NVM) with endurance control

A non-volatile memory device includes an array of non-volatile (NV) memory cells organized in pairs. Each pair is included with a transistor to form a memory unit. Each unit is coupled to a bit line, a word line, and a pair of source lines. The NV elements are programmable to either a relatively high resistance or relatively low resistance and the particularly resistance is established, by converting one resistance type to the other or maintaining the existing resistance type the direction of current through the NV element. A bit is formed from two NV cells in different memory units which are programmed to different resistance types and thereby provide a differential pair from which the logic state of the bit can be determined.

A mechanism for express storage of sensor data in response to an indication of a power fluctuation, power brownout or blackout that can affect operation of a microcontroller is provided. Embodiments provide a flash memory having memory space allocated to express storage of the sensor data, and a protocol machine configured to provide the desired information to reserved registers associated with express program/erase operations accessing the allocated memory space.

Flash memory express erase and program

A technique for detecting an imminent read failure in a memory array includes determining whether a memory array, which does not exhibit an uncorrectable error correcting code (ECC) read during an initial array integrity check at a normal read verify voltage level, exhibits an uncorrectable ECC read during a subsequent array integrity check at a margin read verify voltage level. The technique also includes providing an indication of an imminent read failure for the memory array when the memory array exhibits an uncorrectable ECC read during the subsequent array integrity check. In this case, the margin read verify voltage level is different from the normal read verify voltage level.

Threshold voltage techniques for detecting an imminent read failure in a memory array

A technique for detecting an imminent read failure in a memory array includes determining a first incident count for a memory array that does not exhibit an uncorrectable error correcting code (ECC) read during an array integrity check. In this case, the first incident count corresponds to an initial number of ECC corrections that are performed when the array integrity check of the memory array initially fails. The technique also includes determining a current count for the memory array when the memory array does not exhibit an uncorrectable ECC read during subsequent array integrity checks. In this case, the current count corresponds to a subsequent number of error correcting code (ECC) corrections required during the subsequent array integrity checks. An indication of an imminent read failure for the memory array is provided when the current count exceeds the first incident count by a predetermined amount.

Time-based techniques for detecting an imminent read failure in a memory array

An electronic device can include a first memory cell and a second memory cell. The first memory cell can include a first source, and a second memory cell can include a second source. The first memory cell and the second memory cell can lie within a same sector of a memory array. In one embodiment, erasing the electronic device can include erasing the first memory cell while inhibiting the erase of the second memory cell. A third memory cell can have a third source and lie within another sector. In another embodiment, inhibiting the erase of the first memory cell can include placing the first source and the third source at a same potential. In a particular embodiment, the first source can be electrically insulated from the second source.

Electronic device including a nonvolatile memory array and methods of using the same

A power supply voltage for a memory on an integrated circuit is dynamically adjusted during the operating of the memory. The operating of the memory includes powering the memory at a supply voltage. A test memory of the integrated circuit is concurrently powered while operating the memory. The test memory and the memory each include bit cells of a first bit cell configuration type. A voltage level of the supply voltage is adjusted, while operating the memory, based on the testing of the test memory. The voltage level is adjusted with external variations to assume a value that guarantees no failed operation of the memory but also accurately minimizes the supply voltage. The system and method may be implemented with any type of memory. The memory and test memory may be physically implemented either separated or interspersed on the integrated circuit.

Dynamic voltage adjustment for memory

Integrated testing components and testing algorithm on a non-volatile memory module provide faster Vt (threshold voltage) distributions during the module verification process. The memory module includes address and voltage scanning components and a bit counter for storing the number of 0's or 1's for a specified voltage. As the range of addresses are scanned across a range of voltages, the instances of the count value being counted is accumulated by the bit counter. Automated Tester Equipment (ATE) reads the accumulated count value for each tested voltage.

In-circuit Vt distribution bit counter for non-volatile memory devices

A method for adjusting an operating parameter of an integrated circuit having a memory and logic, where the logic includes a timing circuit, includes accessing the memory, determining a relative speed of the memory access with respect to a speed of the timing circuit, and selectively adjusting the operating parameter based on the relative speed. In one embodiment, an integrated circuit may include a ring oscillator, a shift register having a clock input coupled to an output of the ring oscillator, and compare logic coupled to an output of the shift register. The shift register is enabled in response to initiating a memory access to a memory and disabled in response to completing the memory access. The compare logic provides a relative speed indicator representative of a relative speed of the memory.

Apparatus and method for adjusting an operating parameter of an integrated circuit

A program voltage is applied to the drain electrode of a floating gate transistor to program the floating gate transistor. Concurrent with the application of the program voltage, a current based on the voltage at the source electrode of the floating gate transistor is compared with a threshold current to verify the programming of the floating gate transistor. When the bit cell current falls below the threshold current, the floating gate transistor is considered to be sufficiently programmed and the next floating gate transistor to be programmed is selected. Further, the program voltage supply emulates the selection circuitry used to select between the bit cells so as to model the voltage drop caused by the selection circuitry between the program voltage supply and the drain electrode of the floating gate transistor being programmed. The program voltage supply adjusts the output program voltage based on the modeled voltage drop.

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Austin, TX, United States of America

Thomas Jew