National Semiconductor Corporation

Texas Instruments Corporation

Thomas James Moutinho

Mattias E Dahlstrom

Sergei Drizlikh

Tatsuya Tominari

David Tucker

Wibo Van Noort

Mehmet Emin Aklik

Craig Printy

Ashish Kushwaha

A semiconductor device include a first semiconductor layer with a first doping concentration. A second semiconductor layer has a second doping concentration and has a first surface and a second opposing surface. The second doping concentration is higher than the first doping concentration. The first surface of the second semiconductor layer is in contact with the first semiconductor layer. A contact is on the second surface of the second semiconductor layer. The contact includes a metal and a semiconductor.

Device having multiple emitter layers

A via is formed on a wafer to lie within an opening in a non-conductive structure and make an electrical connection with an underlying conductive structure so that the entire top surface of the via is substantially planar, and lies substantially in the same plane as the top surface of the non-conductive structure. The substantially planar top surface of the via enables a carbon nanotube switch to be predictably and reliably closed.

Via and method of forming the via with a substantially planar top surface that is suitable for carbon nanotube applications

A system and method are disclosed for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process. A tungsten plug is formed in a dielectric layer that overlies a portion of P type silicon and an adjacent portion of N type silicon. The dielectric layer is etched to create a first anti-fuse contact opening down to the underlying P type silicon and a second anti-fuse contact opening down to the underlying N type silicon. A metal layer is deposited over the tungsten plug and over the dielectric layer and etched to form an anti-fuse metal contact in each of two anti-fuse contact openings. A bias voltage is applied to the anti-fuse metal contacts to activate the anti-fuse.

System and method for manufacturing an integrated circuit anti-fuse in conjunction with a tungsten plug process

A process for maintaining a semiconductor substrate layer (e.g. a TiN, W or TEOS) deposition equipment chamber in a preconditioned and low particulate state between successive layer depositions. The first step is determining that the equipment chamber has been in an idle state for more than a first predetermined time period. In the second step, the equipment chamber pressure is reduced to its base pressure in the absence of gas flow, while maintaining the equipment chamber at a first predetermined temperature. In the third step, the equipment chamber is maintained at a second predetermined temperature for a second predetermined time period. During this step, the equipment chamber pressure is held at a first predetermined pressure, while an inert gas is discharged at a first predetermined inert gas flow rate through the equipment chamber. The pressure, time period and gas flow rate in this step are selected in such a way that adequate and thorough heating (i.e. preconditioning) of the equipment chamber and any associated hardware is provided. During the fourth step, the equipment chamber is purged with a inert gas(s) at a second predetermined inert gas flow rate that is greater than the first predetermined inert gas flow rate, to dislodge particulates within the equipment chamber, while maintaining the equipment chamber at a third predetermined temperature. The process sequence from the second step to the fourth step is repeated a predetermined number of times, typically 4 to 6 times. The equipment chamber is then returned to the idle state.

Growing community of inventors

Gorham, ME, United States of America

Thomas James Moutinho