International Business Machines Corporation

Microsoft Technology Licensing, LLC

Thomas James Heller, Jr

Michael Ignatowski

William Todd Boyd

James Walter Rymarczyk

Mark Francis Wilding

Robert J Blainey

Bernard S Meyerson

Richard I Baum

Alexander Abrashkevich

Hung Qui Le

Wayne Frederick Ellis

Howard L Kalter

Matthew Albert Huras

Stanley Everett Schuster

David Meltzer

Richard Edward Matick

Jeffrey H Dreibelbis

Dmitri Abrashkevich

Yogendra K Srivastava

C Brian Hall

Sridhar Munireddy

Richard L Baum

Gottfried Andreas Goldiran

A memory heap management facility is provided that is able to perform various management tasks, including, but not limited to, garbage collection, compaction, and/or re-ordering of objects within a heap. One or more of these management tasks improve system performance by limiting movement of pages in and out of virtual memory. The garbage collection technique selectively performs garbage collection such that certain objects, such as old but live, infrequently referenced objects, are not garbage collected each time garbage collection is performed.

Garbage collection and other management of memory heaps

Embodiments of the present invention provide a method, system and computer program product for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management. In an embodiment of the invention, a method for software prioritization of concurrent transactions for embedded conflict arbitration in transactional memory management can include setting different hardware registers with different priority values for correspondingly different transactions in a transactional memory system configured for transactional memory management according to respective priority values specified by priority assignment logic in external software support for the system. The method also can include detecting a conflict amongst the transactions in the system. Finally, the method can include applying conflict arbitration within the system based upon the priority values specified by the priority assignment logic in the external software support for the system.

Prioritization for conflict arbitration in transactional memory management

Embodiments relate to providing high throughput hardware acceleration. Aspects include initializing an accelerator control queue (ACQ) configured to provide location information on a plurality of pages of data identified as accelerator data. An originating location of each page of requested target data is determined. The originating location includes one of system memory and disk storage. Based on determining that the originating location is system memory, an entry is created in the ACQ mapping to a system memory source address for the target data. Based on determining that the originating location is disk storage, an entry is created in the ACQ mapping to a special pre-stage buffer source address of a special pre-stage buffer for the target data. Each page of the plurality of pages of target data is accessed by the accelerator from respective locations in said memory or said special pre-stage buffer, based on respective entries of the ACQ.

High throughput hardware acceleration using pre-staging buffers

A computing system processes memory transactions for parallel processing of multiple threads of execution with millicode assists. The computing system transactional memory support provides a Transaction Table in memory and a method of fast detection of potential conflicts between multiple transactions. Special instructions may mark the boundaries of a transaction and identify memory locations applicable to a transaction. A 'private to transaction' (PTRAN) tag, directly addressable as part of the main data storage memory location, enables a quick detection of potential conflicts with other transactions that are concurrently executing on another thread of said computing system. The tag indicates whether (or not) a data entry in memory is part of a speculative memory state of an uncommitted transaction that is currently active in the system. Program millicode provides transactional memory functions including creating and updating transaction tables, committing transactions and controlling the rollback of transactions which fail.

Computing system with transactional memory using millicode assists

A method () or a diagnostic recording device () having transactional memory and a processor coupled to the transactional memory can store () contents of a transaction log () of the transactional memory, detect () an exception event, and replay () last instructions that led up to the exception event using a debugger tool (). The transactional memory can be hardware or software based transactional memory. The processor can also store the transaction log by storing the contents of the transaction log in a core file () which can include a stack (), a register dump (), a memory dump (), and the transactional log. The debugger tool can be used to load up the core file, an executable file (), and a library () to enable the diagnostic recording device to retrace transactions occurring at the diagnostic recording device up to the exception event.

Method and apparatus for diagnostic recording using transactional memory

Program execution with improved power efficiency including a computer program that for performing a method that includes determining a current power state of a processor. Low power state instructions of an application are executed on the processor in response to determining that the current power state of the processor is a low power state. Executing the low power state instructions includes collecting hardware state data, storing the hardware state data, and performing a task. High power state instructions of the application are executed on the processor in response to determining that the current power state of the processor is a high power state. Executing the high power state instructions includes performing the task using the stored hardware state data as an input.

Program execution with improved power efficiency

Embodiments related to a hardware transactional memory (HTM). An aspect includes setting a mode register of a processor core of a computer to indicate a HTM mode. Another aspect includes executing a plurality of transactions by the processor core in the HTM mode based on the mode register. Another aspect includes determining whether a first transaction of the plurality of transactions exceeds a failure limit of the processor core in the HTM mode. Yet another aspect includes, based on determining that the first transaction exceeds the failure limit of the processor core in the HTM mode, transitioning the processor to an assisted transaction mode by setting the mode register of the processor core to indicate the assisted transaction mode.

Hybrid Transactional Memory (HybridTM)

A multiple-core processor supporting multiple instruction set architectures provides a power-efficient and flexible platform for virtual machine environments requiring multiple support for multiple instruction set architectures (ISAs). The processor includes multiple cores having disparate native ISAs and that may be selectively enabled for operation, so that power is conserved when support for a particular ISA is not required of the processor. The multiple cores may share a common first level cache and be mutually-exclusively selected for operation, or multiple level-one caches may be provided, one associated with each of the cores and the cores operated as needed, including simultaneous execution of disparate ISAs. A hypervisor controls operation of the cores and locates a core and enables it if necessary when a request to instantiate a virtual machine having a specified ISA is received.

Multiple-core processor supporting multiple instruction set architectures

A method for controlling the allocation of shared resources that includes receiving, from a requestor executing on a processor, a request to access a shared resource. The receiving is at a next request priority module connected to the processor and the shared resource. It is determined if any of a specified number of most recent priority grants to the shared resource were to the requestor. The request is granted if none of the specified number of most recent priority grants to the shared resource were to the requestor. If any of the specified number of most recent priority grants to the shared resource were to the requestor, then it is determined if one or more other requests for the shared resource are pending. It is determined if one of the other requests should be granted priority to the shared resource if other requests for the shared resource are pending.

Microprocessor with software control over allocation of shared resources among multiple virtual servers

Embodiments related to a transaction program. An aspect includes, based on determining that one instruction is part of an active atomic instruction group (AIG), determining whether a private-to-transaction (PTRAN) bit associated with an address of the one instruction in a main memory is set, the PTRAN bit being located in a main memory comprising a plurality of memory increments each having a respective directly addressable PTRAN bit in the main memory. Another aspect includes, based on determining that the PTRAN bit is not set: setting the PTRAN bit; adding a new entry to a cache structure and a transaction table including an old data state of the address of the one instruction stored in the cache structure and control information stored in the transaction table; and completing the one instruction as part of the active AIG.

Transactional memory system with efficient cache support

A data structure of readily accessible units of memory is provided as computer useable media having computer readable program code logic providing information tables and a software emulation program to enable hardware to run new software that uses transactional memory and a bit associated with a transaction for executing transactional memory constructs. The data structure with Guest PTRAN bit is used in emulation of software written for a given computer on a different computer which executes a different set of instructions. The emulating instructions are used to provide transactional memory instructions on a computer which does not support those instructions natively.

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Rhinebeck, NY, United States of America

Thomas James Heller, Jr