Xilinx, Inc.

Koninklijke Philips Corporation N.v.

Thomas James Davies

Henry A Om'Mani

Schuyler E Shimanek

Eric E Edwards

Roy D Darling

Jesse H Jenkins, Iv

Shankar Lakkapragada

Guoqiao Tao

Frank C Wirtz, Ii

Robertus Dominicus Joseph Verhaar

Henry A Om'mani

Johannes Dijkstra

An integrated circuit system () includes a memory array () storing a configuration data set to configure an integrated circuit. The integrated circuit () includes a configuration memory () and a configuration controller state machine (). The configuration controller state machine operates so as to read a read-check signature at a read-check address of the memory array () and to compare the read-check signature with a standard signature stored in the integrated circuit (). If the read-check signature passes the comparison, the configuration controller state machine () loads the configuration data set from the memory array to the configuration memory () of the integrated circuit.

Non-volatile memory read-check

Method and apparatus for providing secure programmable logic devices is described. One aspect of the invention relates to securing a programmable logic device having instruction register logic coupled to control logic via an instruction bus. A non-volatile memory is provided for storing at least one security bit for at least one instruction associated with the programmable logic device. Gating logic is provided in communication with the non-volatile memory and at least a portion of the instruction bus. The gating logic is configured to selectively gate decoded instructions transmitted from the instruction register logic towards the control logic based on state of the at least one security bit.

Method and apparatus for providing secure programmable logic devices

Described are area-efficient non-volatile memory systems. Non-volatile memory cells in these systems include only one transistor, two fewer than conventional non-volatile memory cells, and reduced interconnect. The simplicity of the memory cells reduces memory-system area, improves manufacturing yield, and consequently reduces cost. New program, erase, and read methodologies have been developed for use with the simplified memory cells.

Single transistor non-volatile memory system, design, and operation

A non-volatile product term cell is provided having a first floating gate located over a first p-channel transistor and a first n-channel transistor, and a second floating gate located over a second p-channel transistor and a second n-channel transistor. A control gate is located over the first and second floating gates. A first tunnel oxide capacitor is coupled to the first floating gate and a second tunnel oxide capacitor is coupled to the second floating gate. A first transistor pair is coupled between the first p-channel transistor and the second n-channel transistor, and a second transistor pair is coupled between the second p-channel transistor and the first n-channel transistor. The first and second floating gates are programmed and/or erased. Complementary input signals are applied to the first and second transistor pairs. An output signal is provided in response to the programmed/erased states of the first and second floating gates.

Non-volatile product term (pterm) cell

A CPLD employs a low-voltage, non-degenerative transmitter circuit to eliminate the need for a dedicated control pin to provide the relatively high voltage levels required to verify the program states of programmable memory cells. Eliminating the need for a dedicated control pin frees up valuable chip real estate for the inclusion of an additional general-purpose input/output pin.

Low-voltage non-degenerative transmitter circuit

A level shifter for low voltage operation includes two level shifting stages. The first stage shifts the input voltage level to an intermediate voltage level, and the second stage shifts the intermediate voltage level to an output voltage level. This two-stage arrangement allows the level shifter to function for very low input voltages, and enables functionality across a wide range of output voltages. The first stage is designed to be compatible with very low input voltages and the intermediate voltage level is chosen to be within the safe operating limits of the first stage. The intermediate voltage level is also high enough to drive the high voltage devices of the second stage. This level shifter can be used where multiple output voltage levels are required depending on the particular application or operating mode.

Dual stage level shifter for low voltage operation

Described are circuits and methods for automatically measuring the program threshold voltage V and the erase threshold voltage V of EEPROM cells. The measured threshold voltages are employed to measure tunnel-oxide thickness and to determine optimal program and erase voltage levels for EEPROM circuits. One embodiment automatically sets the program and erase voltages based on the measured threshold voltages.

Automatic program- and erase-voltage generation for EEPROM cells

A method for reconfiguring a complex programmable logic device (CPLD) that includes an EEPROM array and a shadow SRAM array comprises reprogramming the EEPROM array with new configuration data while the CPLD is operating in a first configuration. This relatively time-consuming operation has no effect on CPLD operation since only the SRAM array controls the configuration of the CPLD. At a desired point in time, the new configuration data from the EEPROM array can be loaded into the SRAM array to reconfigure the CPLD. Because this loading of configuration data into the SRAM array takes only microseconds to perform, normal system operation effectively proceeds without interruption. A CPLD can include multiple EEPROM arrays, each storing a different set of configuration data, thereby allowing the CPLD to rapidly switch between various configurations by loading the configuration data from different EEPROM arrays into the SRAM array.

Programming on-the-fly (OTF)

A ramp-up circuit on an integrated circuit receives a relatively high program (erase) voltage for changing the program state of a memory cell. The ramp-up circuit gradually raises the program (erase) voltage to prevent damage to the memory cell. The ramp-up circuit includes a pass gate and associated control circuitry that provides a controlled, ramped-up version of the program (erase) voltage to the memory cell without raising internal circuit nodes above the program (erase) voltage.

Growing community of inventors

Albuquerque, NM, United States of America

Thomas James Davies