Mediatek Corporation

Analog Devices,inc.

Thomas James Barber, Jr

Aiguo Yan

Marko Kocic

Lidwine Martinot

John Zijun Shen

Jeffrey Carl Gealow

Paul Donald Krivacek

Stacy Ho

Paul F Ferguson, Jr

Joern Soerensen

Palle Birk

Paul F Ferguson

Xavier S Haurie

A joint detection system is configured to perform joint detection of received signals and includes a joint detection accelerator and a host processor. The joint detection accelerator may include a memory unit to store input data values, intermediate results and output data values; one or more computation units to process the input data values and the intermediate results, and to provide output data values to the memory unit; a controller to control the memory and the one or more computation units to perform joint detection processing; and an external interface to receive the input data values from the host processor and to provide output data values to the host processor. The computation units may include a complex multiply accumulate unit, a simplified complex multiply accumulate unit and a normalized floating point divider. The memory unit may include an input memory, a matrix memory, a main memory and an output memory.

Architecture for joint detection hardware accelerator

A joint detection system and associated methods are provided. A joint detection system is configured to perform joint detection of received signals. The joint detection system includes a joint detector accelerator configured to perform an operation of the joint detection of the received signals, wherein the joint detection includes computing joint detection variables. The operation includes a multiply and accumulate operation resulting in a value in an accumulator, and the value in the accumulator includes a plurality of bits. The joint detector accelerator is configured to select a subset of bits of the plurality of bits of the value in the accumulator, where the subset of bits selected is configurable. The joint detector accelerator is further configured to store the subset of bits into a memory as a fixed point representation.

Fixed-point implementation of a joint detector

A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals. The joint detection system includes a programmable digital signal processor (DSP) configured to generate initial channel estimates corresponding to propagation channels, wherein each of the initial channel estimates includes a plurality of values. The programmable DSP is further configured to determine one or more pre-scaling factors for one or more of the initial channel estimates. The pre-scaling factors are at least partially based on at least one of the plurality of values of one or more of the initial channel estimates. The programmable DSP is further configured to pre-scale the initial channel estimates by the pre-scaling factors.

Pre-scaling of initial channel estimates in joint detection

A joint detection system and associated methods are provided. The joint detection system is configured to perform joint detection of received signals and includes a joint detector accelerator and a programmable digital signal processor (DSP). The joint detector accelerator is configured to perform front-end processing of first data inputted to the joint detector accelerator and output second data resulting from the front-end processing. The joint detector accelerator is further configured to perform back-end processing using at least third data inputted to the joint detector accelerator. The programmable DSP is coupled to the joint detector accelerator, and the programmable DSP is programmed to perform at least one intermediate processing operation using the second data outputted by the joint detector accelerator. The programmable DSP is further programmed to output the third data resulting from the intermediate processing operation to the joint detector accelerator.

Method and apparatus for joint detection

A clock enable system for a multichip device includes a first integrated circuit including a clock signal and at least a second integrated circuit including at least one functional block periodically requiring clock signals from the first integrated circuit; a clock required circuit responsive to each functional block for providing a clock required signal in response to activation of any one or more of the functional blocks; and a clock enable circuit responsive to the clock required signal for enabling the first integrated circuit to provide clock signals to the functional blocks on the second integrated circuit.

Clock enable system

A multimode voltage regulator includes a low current pass device and a high current pass device each adapted for connection between a power supply and a load; an error amplifier responsive to a difference between a reference voltage and a function of the voltage on the load to produce an error signal; and a low power driver responsive in a low load power mode to an error signal for operating the low current pass device to provide low power to the load and a high power driver responsive in a high load power mode to an error signal for operating the high current pass device to provide high power to the load for maintaining efficiency over high and low power load operation.

Multimode voltage regulator

A voltage regulator with dynamically boosted bias current includes a pass device for providing current to a load; an error circuit responsive to a difference between a predetermined reference voltage and a function of the voltage on the load to produce an error signal, a driver circuit responsive to the error signal for controlling the pass device to adjust the current to the load to reduce the error signal, the driver circuit including an amplifier responsive to the error signal for controlling the pass device, a bias current source for biasing the amplifier, a sensing circuit for sensing a portion of the error signal, a reference current source for providing a reference current, a second error circuit responsive to a difference between the portion of the error signal and the reference current to produce a second error current; and a boost circuit responsive to the second error signal to increase the bias current provided to the amplifier when the load demands more current.

Voltage regulator with dynamically boosted bias current

An offset calibration system includes an analog to digital converter having a first full-scale range with a first offset compensation circuit; a digital to analog converter having a second full-scale range with a second offset compensation circuit; the digital to analog converter having its output connected to the input of the analog to digital converter during calibration of the digital to analog converter; and a range adjustment circuit for accumulating a predetermined number of analog to digital output values and dividing the accumulated values by a preselected power of 2 in the ratio of the voltage corresponding to the analog to digital converter least significant bit to the voltage corresponding to the digital to analog converter least significant bit.

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Bolton, MA, United States of America

Thomas James Barber, Jr