Harris Corporation

Other

Thomas J Sanders

William R Morcom

Jacob A Davis

William H White

Nicolaas W Van Vonno

Clyde Combs

Glenn T Hess

A combination clothes dryer and air filter. The device is adapted for reversal of airflow through a housing to allow a horizontal position and a vertical position for operation. The device is adapted for easy storage in the horizontal position.

Combination air purifier and clothes dryer

A PIN diode-based monolithic Nuclear Event Detector and method of manufacturing same for use in detecting a desired level of gamma radiation, in which a PIN diode is integrated with signal processing circuitry, for example CMOS circuitry, in a single thin-film Silicon On Insulator (SOI) chip. The PIN diode is implemented in the p-substrate layer. The signal processing circuitry is located in a thin semiconductor layer and is in electrical communication with the PIN diode. The PIN diode may be integrated with the signal processing circuitry onto a single chip, or may be fabricated stand alone using SOI methods according to the method of the invention.

Monolithic nuclear event detector and method of manufacture

A vertical bipolar transistor including a base having impurity concentration equal in order of magitude to and being formed in the surface of an emitter, a collector having impurity concentration at least two orders of magnitude greater than and being formed in the surface of the base, and a ring having the same impurity conductivity type as the base, having impurity concentration at least three orders of magnitude greater than the base's and being formed at the junction of and in the surfaces of the base and emitter. The ring extends from the surface at to least the depth of the collector and not greater than the depth of the base.

Radiation hard, high emitter-base breakdown bipolar transistor

A radiation hardened CMOS formed by applying a radiation hard gate oxide layer on a silicon substrate, applying silicon doped aluminum gates on the gate oxide, and by ion implanting and annealing source and drain regions using said gates as masks at a temperature of or below 500 degrees centigrade. Using an N.sup.- type substrate, a P.sup.+ guard ring is formed at the interface of the P.sup.- well of the N channel MOS device and the N.sup.- substrate before the formation of the gate oxide.

Radiation hardened-self aligned CMOS and method of fabrication

A radiation hardened CMOS formed by applying a radiation hard gate oxide layer on a silicon substrate, by applying silicon doped aluminum gates on the gate oxide, and by ion implanting and annealing source and drain regions using said gates as masks at a temperature of or below 500 degrees centigrade. Using an N.sup.- type substrate, a P.sup.+ guard ring is formed at the interface of the P.sup.- well of the N channel MOS device and the N.sup.- substrate before the formation of the gate oxide.

Method of fabricating improved radiation hardened self-aligned CMOS

A metallic ground grid is fabricated by forming a conductor on the isolation barrier of an integrated circuit through openings in a first insulated layer to a depth less than the first insulated layer, forming a second insulated layer on said first conductor to the height of the first insulated layer, and interconnecting selected areas of the integrated circuit and the first conductor through openings in the insulated layers by a second conductor.

Process for forming metallic ground grid for integrated circuits

In a process for fabricating complementary FETS, wherein a first insulative layer has apertures therein, a second insulative layer doped with N-type impurities is formed over the area in which an N channel device is to be formed and is diffused in a non-oxidizing atmosphere through apertures in the first insulative layer to form the source and drain of an N channel device. Immediately thereafter, an atmosphere containing a P-type impurity is introduced to deposit and diffuse P-type impurities through exposed apertures in the first insulative layer to form the source and drain of a P channel device.

Process for fabricating diffused complementary field effect transistors

Isolation of device locations in a monolithic semiconductor integrated circuit is provided by depositing a thin film effective as a polishing stop on a planar surface of the semiconductor body in which the devices are to be fabricated, etching isolation grooves into the body through the thin film, coating the surfaces of the grooves and the film with an insulator layer, and growing polycrystalline material over the insulator layer to fill the grooves. The polycrystalline material in excess of that required to fill the grooves, and any insulator layer covering the planar surface of the thin film, are polished away without affecting the underlying planar surface of the semiconductor body, because the thin film is adapted to withstand polishing without damage. Finally, the thin film is stripped away leaving semiconductor islands having a planar surface and isolated by insulator layer-polycrystalline material filled moats. Devices are fabricated in these islands.

Device isolation in integrated circuits

A metallic ground conductor grid applied over a planar isolation barrier in an integrated circuit provides a low resistance ground. An insulating layer, formed over the ground conductor, has apertures therein for interconnecting selected areas of the integrated circuit to the ground conductor grid.

Metallic ground grid for integrated circuits

An integrated circuit having a metal interconnect system formed with molybdenum engaging all contact areas of N conductivity type regions and aluminum engaging said molybdenum and engaging all contact areas of P conductivity type regions.

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Indialantic, FL, United States of America

Thomas J Sanders