Advanced Micro Devices Corporation

Broadcom Corporation

Other

Thomas J Runaldue

Bahadir Erimli

Chandan Egbert

Denise Kerstein

Ian S Crayford

Peter Ka-Fai Chow

Yi Cheng

Jayant Kadambi

Philip Simmons

Glen Gibson

William C Plants

Ching Yu

Jeffrey Roy Dwork

Jinqlih Sang

Eric Tsin-ho Leung

Sambun Boun

Dinesh Mahale

Matthew James Fischer

Shashank C Merchant

Somnath Viswanath

Eric Tsin-Ho Leung

Qazi R Mahmood

Philip Ngai

Patrick Green

Ronald Bianchini, Jr

A network hub in a communication network that acts as a server to network clients to push, or transmit, information regarding the state of local and remote devices and networks. The information can be one, or more, status information, which information can be one or more predefined fields in a frame, which represents a packet of data. In one embodiment, it is desirable that the frame be a 'legitimate' Ethernet-type frame. The status field can be a 'push'-Type status field. The push operation can be a unicast, a multicast, or a broadcast, or a hybrid transmission. The hub can be a switch, repeater, a bridge, a router, a gateway, or a hybrid thereof. Also, the hub according to the present invention can be an OSI Layer 2 device, an OSI Layer 3 device, or a hybrid thereof. It is desirable that the hub be devoid of a microprocessor. As described herein, the hub may have plural ports, for example, four, eight, or more ports.

Method and apparatus for a network hub to diagnose network operation and broadcast information to a remote host or monitoring device

A clock generation system includes an oscillator and one or more clock generators. The oscillator provides inphase and quadrature oscillator signals having a fixed frequency. Each clock generator receives the oscillator signals and generates a respective output clock signal. Within each clock generator, two weight generators receive two sequences of phase values and generate weights for two analog signals. Two signal generators multiply the inphase and quadrature oscillator signals with the weights from the two weight generators and provide the two analog signals having leading edges determined by the two sequences of phase values. A digital clock generator generates a DCLK signal based on the two analog signals. A divider divides the DCLK signal by N in frequency and provides the output clock signal. A phase generator generates the two sequences of phase values for the two analog signals based on a frequency control value and a phase offset value.

Clock generation with continuous phase

An integrated multiport switch (IMS) having a receive FIFO structure with a single port RAM, for storing network communication data received from each port of the switch. The RAM is connected to a FIFO control unit, which is coupled to a MAC for each port by a MAC bus, by a FIFO memory input bus. Writing of data received from each port via the MAC bus to the RAM is controlled on a time shared basis. The FIFO control unit includes a receive RAM interface that is connected to the MAC bus for receiving communication data from the ports and to the FIFO memory input bus for transferring communication data to the RAM for temporary storage. As the FIFO memory input bus has a larger bit transfer capacity than the MAC bus, the receive RAM interface can accumulate incoming data during clock cycles in which data is being read from the single port RAM. When the accumulated data for a given port is to be written to the RAM in a subsequent write cycle, it is then combined with additional incoming data for the same port received at that time for transfer to the RAM.

Integrated multiport switch having shared data receive FIFO structure

A method and arrangement for reclaiming buffers used to store frames, following the transmission of a frame, checks to determine whether the transmission of a frame is the last copy of that frame to be transmitted. If it is the last copy, or the only copy, the buffers storing that frame are reclaimed for reuse after the contents of each buffer are transmitted. If the frame is not the last copy, or it cannot be determined whether it is the last copy, then the frame is transmitted and a count of the number of transmitted copies of that frame is decremented. Once all of the copies have been transmitted, the buffer reclaiming process is initiated.

Method and apparatus for reclaiming buffers

A resetting, enabling and freezing system is provided for controlling a communication device in a diagnostic process. A hardware reset of the device may be performed by a host via a reset pin of a PCI interface. A software reset of the device may be provided by setting a reset bit in a command register. To stop operations of the device substantially instantaneously, a freeze mode of diagnostics is provided. The freeze mode may be initiated using hardware or software freezing. To provide the hardware freezing, diagnostic logic is supplied with a freeze signal via a freeze pin of the PCI interface. The software freezing is performed by setting a freeze bit in the command register. To enable a diagnostician to reproduce an event causing an error, an enable/disable mode of diagnostics is carried out. In this mode, elements of the device are disabled one after another in a serial fashion, with a disable signal being passed serially from one element to another. After the elements are disabled, they may be set into a chosen state to recreate a required event.

Method and apparatus for resetting, enabling and freezing a communication device in a diagnostic process

A network switch having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on a selected network port. The network switch includes a queue for storing free frame pointers, each specifying available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated on a half-duplex network port by transmitting a phantom packet to a transmitting network station if the output buffer of a destination port exceeds a programmed high threshold, or if the output buffer of the destination port exceeds a low programmed threshold and the queue of free frame pointers falls below a low programmable threshold. The switch thus provides flexibility in providing selective collisions with transmitting stations to minimize the possibility of network congestion without wasting network bandwidth with unnecessary collisions.

Method and apparatus providing programmable thresholds for half-duplex flow control in a network switch

Write posting buffers and read prefetch buffers are arranged in an integrated multiport switch between a PCI interface and an external memory interface. When a PCI host initiates a PCI transaction to write data from an external memory, the data provided by the PCI host is written into the write posting buffers. Then, the contents of the write posting buffers is transferred to the external memory. The read prefetch buffers are used to temporarily store data prefetched in anticipation of a PCI transaction initiated by the PCI host to read that data from the external memory. When the PCI host initiates the read transaction, the address of the requested data is compared with the address of the prefetched data to transfer the prefetched data to the host if a match is detected. In an auto-prefetch mode, data is automatically prefetched from the external memory when an extension bus port output queue contains a frame pointer for a frame queued for transmission over the PCI interface to the PCI host.

Method and apparatus for prefetching data read by PCI host

A method and arrangement for maintaining a time order of entries in a memory determines a row in which the entry will be stored, the memory being logically divided into rows and columns. The columns are arranged sequentially in each row from the newest to the oldest. Once the row in which the entry will be stored is determined, the entry is stored in that row in the column (or entry location) that is the newest column. The entry that was previously in the newest column is shifted to the next older column, and the entry that was previously in the next older column is shifted to the next most older column, etc. If a row is completely filled prior to the writing of a new entry, then the entry in the oldest column is removed from the memory and the other entries shifted.

Method and apparatus for maintaining a time order by physical ordering in a memory

An integrated multiport switch (IMS) for a data network has a management port for direct communication with an external management agent. The switch, which is integrated into a single chip, includes a management interface that comprises logic circuit elements. This interface acts as a virtual physical layer for both the media access controller (MAC) at the management port and the MAC at the external management agent. The latter may be located on the same circuit board as the IMS chip. PHY devices for these MACs are eliminated while the collision signal and carrier sense signal generation functions are maintained. The PHY devices are replaced by a logic interface while permitting use of the standard Simplified Network Management Protocol (SNMP) software for the interfacing operations. No modification of MAC software is required.

Multiport data network switch having direct media access control link to external management

A network having a shared memory architecture for storing data frames has a set of programmable thresholds that specify when flow control should be initiated on full-duplex network ports. The network switch includes a queue for storing free frame pointers that specify available memory locations in an external memory for storing data frames received from a network station. The network switch takes a frame pointer from a free buffer queue for each received data frame, and stores the received data frame in the location in external memory specified by the frame pointer while a decision making engine within the switch determines the appropriate destination ports. Flow control is initiated based on the number of available frame pointers by transmitting a PAUSE frame having a selected PAUSE interval to a transmitting network station. Specifically, a full-duplex port will output a PAUSE frame having a short, medium, or long programmed pause interval if the free buffer pool of available frame pointers falls below a high, medium, or low programmable threshold, respectively. The switch thus provides flexibility in generating variable-length PAUSE control frames to minimize wasting network bandwidth.

Method and apparatus providing programmable thresholds for full-duplex

A driver having a switchable gain including a first circuit connected to a potential source, an input node receiving an input current, and an output node and operable in both low and high transmission frequency modes, and a second circuit connected to the potential source and a node of the first circuit and operable in only the high transmission frequency mode. In the low transmission frequency mode, the potential source is at a first level and the first circuit receives the input current and provides a first output current with a first current gain to the output node. In the high transmission frequency mode, the potential source is at a second, lower level and the first and second circuits receive the input current and provide a second output current, less than the first output current, with a second current gain, lower than the first current gain, to the output node.

Driver with switchable gain

A novel auto-negotiation system capable of performing auto-negotiation using negative link pulses. The auto-negotiation system operates in a network transceiver for interconnecting multiple hub communication devices having different operating speeds and link partners provided on a transmission medium. The network transceiver comprises physical layer devices for supporting data exchange between the hub devices and the link partners, and an auto-negotiation device that transmits and receives link pulses of a prescribed polarity carrying auto-negotiation information to and from the link partners to select a mode of communication between the hub devices and the link partners. A reverse polarity detection and correction circuit is provided for supporting auto-negotiation operations when link pulses received from a link partner have a reverse polarity. In a preferred embodiment, the reverse polarity detection and correction circuit comprises a polarity detector for detecting polarity of the link pulses received from the link partner, and a link pulse detector for distinguishing link pulses from data received from the link partner. A polarity reversing circuit responsive to the polarity detector and the link pulse detector reverses polarity of the received link pulses.

Auto-negotiation using negative link pulses

A method and arrangement for transmitting multiple copies of a frame from a network switch in a packet switched network stores a single copy of the frame received at the switch into external memory. The frame is stored at a location in memory pointed to by a frame pointer. In queuing multiple transmissions of the stored frame in the switch, the frame pointer, and not the frame itself, is replicated and queued for transmission in the network switch.

Method and apparatus for transmitting multiple copies by replicating

A data communication device having multiple ports is provided with an auto-negotiation system for performing auto-negotiation with multiple link partners connected to the ports. The auto-negotiation system has a memory and an auto-negotiation unit including transmit, receive and arbitration state machines for performing transmit, receive and arbitration state diagrams compliant with the IEEE 802.3 Standard. The auto-negotiation unit operates in a time-division multiplexing mode using successive time slots for supporting auto-negotiation operations for different ports. The memory is used for storing state diagram variables for a port in a time interval between the time slots assigned to that port.

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San Jose, CA, United States of America

Thomas J Runaldue