Silicon Graphics, Incorporated

Mips Computer Systems, Inc.

Point Somee Limited Liability Company

Mips Technologies, Inc.

Quantum Effect Design, Inc.

Aril Computer Corporation

Wuantum Effect Design, Inc.

Thomas J Riordan

Earl A Killian

Paul S Ries

Albert M Thaik

Anatoly Shteynberg

Harry Rodriguez

Dongsheng Zhou

Bradley M Lehman

Stephen F Dreyer

Mark Eason

John R Kinsel

Craig C Hansen

Danny L Freitas

Ashish B Dixit

John L Hennessy

Sinan Doluca

Larry B Weber

Steven A Przybylski

Edwin L Hudson

Hai N Nguyen

Sunil Mirapuri

An eight-transistor (8T) Static Random-Access Memory (SRAM) cell has four latch transistors, and pairs of n-channel and p-channel pass transistors in parallel to only one pair of bit lines. During read, only the read word line and the n-channel pass transistors are activated, but during a write both the read word line and an extra write word line are activated to turn on all four pass transistors. The cell is powered by VDDM, one threshold above the normal VDD power supply of the read sense and write drivers and interfaces. The bit lines are precharged to VDD but pulled up to VDDM by a latch of cross-coupled p-channel transistors. Any p-channel transistors that connect to the bit lines are driven inactive by VDDM. The read margin is largely decoupled from the write margin by two additional p-channel pass transistors and one extra word line versus a standard 6T cell.

Ultra-low supply-voltage static random-access memory (SRAM) with 8-transistor cell with P and N pass gates to same bit lines

An apparatus, method, and system are disclosed for providing AC line power to lighting devices such as light emitting diodes ('LEDs'). A representative apparatus comprises: a plurality of LEDs coupled in series to form a first plurality of segments of LEDs; a plurality of switches coupled to the plurality of segments of LEDs to switch a selected segment into or out of a series LED current path in response to a control signal; a current sensor; and a controller which, in response to a first parameter and during a first part of an AC voltage interval, generates a first control signal to switch a corresponding segment of LEDs into the series LED current path; and during a second part of the AC voltage interval, generates a second control signal to switch the corresponding segment of LEDs out of the first series LED current path.

Apparatus, method and system for providing AC line power to lighting devices

An apparatus, method, and system are disclosed for providing AC line power to lighting devices such as light emitting diodes ('LEDs'). A representative apparatus comprises: a plurality of LEDs coupled in series to form a first plurality of segments of LEDs coupled in series; a plurality of switches coupled to the plurality of segments of LEDs to switch a selected segment into or out of a series LED current path in response to a control signal; a memory; and a controller which, in response to a first parameter and during a first part of an AC voltage interval, determines and stores in the memory a value of a second parameter and generates a first control signal to switch a corresponding segment of LEDs into the series LED current path, and during a second part of the AC voltage interval, when a current value of the second parameter is substantially equal to the stored value, generates a second control signal to switch a corresponding segment of LEDs out of the first series LED current path.

Techniques for matching the speed of a microprocessor to potentially slower external system components. A master clock signal is communicated to a clock generator on the processor chip. The clock generator provides at least one external clock signal, which is communicated to various portions of the system. The clock generator includes programmable clock division circuitry that allows the external clock signal to be generated at any selected one of a plurality of fractions of the master clock frequency. The data pattern (the particular cycles in a sequence during which the processor outputs a data word as part of a multiple-data-word sequence) is programmable independently of the external clock programming.

Processor chip for using an external clock to generate an internal clock

A structure and a method are provided in a table lookaside buffer (TLB) for translating a virtual memory address to a physical memory address. The virtual memory address is computed by adding to a base address an offset value. In the TLB of the present invention, each entry of the TLB is stored a previous base address, a partial sum of the previous virtual memory address computation, the sign bit of the previous offset value, and the value of the carry bit at the position of the sign bit of the previous offset value in the previous virtual memory address computation. The present invention is especially applicable to a data TLB used in conjunction with a two-way set associative data cache memory.

Processor with an efficient translation lookaside buffer which uses

Processor chip having on-chip circuitry for generating a programmable

Structure and method for virtual-to-physical address translation in a

A method and apparatus for restarting an instruction processing pipeline after servicing one or more interlock processing faults. A pipeline architecture is defined in which processing interdependencies (such as instruction latencies, resource conflicts, cache accesses, virtual address translations and sign extend operations) are presumed not to be present so as to increase pipeline throughput. Interdependencies which actually occur appear as processing faults which then are serviced. At the completion of the servicing, pipeline restarting operations occur, during which the portions of the pipeline which are invalidated are preloaded. Preloading includes backing-up the invalidated stages and re-executing such stages with corrected information so as to fill the pipeline. The pipeline portions (e.g., stages) which are invalidated are determined by the type of processing fault which occurs. Upon completion of preloading, normal instruction pipeline processing resumes.

Method and apparatus for retarting pipeline processing

A technique for extending the data word size and the virtual address space of a pre-existing architecture so that hardware for the extended architecture also supports the pre-existing architecture. Extension of the data word size from m bits to N bits entails widening the machine registers and data paths from m bits to N bits and sign-extending entities of m or fewer bits to N bits when they are loaded into registers. Some of the m-bit instructions, when operating on N-bit sign-extended versions of m-bit entities, produce an N-bit result that may not correspond to the correct m-bit result, sign-extended to N bits. For these instructions compatibility requires that the instructions be further defined to guarantee a sign-extended result. This means that separate N-bit instructions corresponding to these m-bit instructions are needed. The support for up to an N-bit virtual address space is provided in part by widening the virtual address data paths. The extended architecture supports the m-bit architecture's addressing with minimal additional hardware. This is made possible by storing m-bit addresses as N-bit entities in sign-extended form and requiring that the results of address computations on these entities be in sign-extended form.

Backward-compatible computer architecture with extended word size and

Techniques for providing a number of precisely synchronized clock signals at a number of different frequencies at each of a plurality of locations on a chip. A number of synchronized clock signals are generated at an initial location on the chip, and distributed to the various locations with relative delay times that are equal to within a precision, which may be less than the ultimate precision required. A single synchronization signal is also generated at the initial location, and is distributed to the remote locations with delay times that are equal to each other to a precision that corresponds to the precision required of all the clock signals. Separate synchronization circuitry at each remote location receives the clock signals and the synchronization signal, and resynchronizes the clock signals to the precision with which the synchronization signal was distributed. The set of lines is configured as a tree structure. The clock generation system has a cycle-down mode wherein all the clock frequencies are divided by a desired divisor. The frequency division occurs in response to a cycle-down signal, but the different clock frequencies are not switched until all have their rising edges aligned. The result is that the state of the machine is preserved when the clocks are cycled down.

Clock distribution system for an integrated circuit device

A translation look-aside buffer with a variable page size per entry is disclosed. Each entry can have a different number of bits translated from a virtual address to a physical address. Each entry in the TLB contains an indication of the page size for that entry. When the translation is done, the indication of page size determines how many bits are translated.

Variable page size per entry translation look-aside buffer

A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.

Processor controlled interface with instruction streaming

A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme is accessible from outside the physical package(s) in which the functional unit is housed. The data order conversion unit may comprise a load aligner and/or a store aligner, one or both of which may comprise means for shifting informational units of a smaller size within informational units of a larger size. The shift amount may derive from the low order address bits and may be altered depending on the external data ordering means selected.

Dual byte order computer architecture a functional unit for handling

In a RISC device a set of four instructions are provided which allow either the loading or the storage of an unaligned reference. The instructions are overlapped to reduce the overall execution time of the device. A circuit is also provided for executing the instruction set.

Growing community of inventors

Los Altos, CA, United States of America

Thomas J Riordan