Gte Automatic Electric Incorporated

Gte Automatic Electric Labs Inc.

Ag Communication Systems Corporation

Other

Gte Communication Systems Corporation

Thomas J Perry

Michel Loos

Joseph A Comfort

Muhammad I Khera

Robert E Renner

Randall L Brown

James B Southway, Jr

James F Hoff

Frank Sciabica

John Wesley Spenik

Satrio P Mualim

Christopher M Burlingame

Scott J Baer

Kevin B Plyler

Jeffrey Glenn Hunt

Michael Gilbert

Rene LeBlanc

Kevin B Plyer

James B Southway

John W Spenik

A system that provides secure transmission of data between a subscriber's PC and an online service provider (OLS) over an Ethernet WAN. The system includes a remote transceiver unit located at a subscriber site and connected to the subscriber's PC; a central transceiver unit located at a telephone central office and connected to the remote transceiver unit over a twisted pair network and also connected to a WAN; an authorization server that is connected to the WAN; and one or more OLSs, which may include Internet service providers, connected to the WAN. Security of transmission is provided through a method in which only subscriber transmissions directed to a session-specific OLS are allowed to pass through the central transceiver unit onto the WAN, and only unicast transmissions from authorized OLSs are allowed to pass through the central transceiver unit to the subscriber port of the remote transceiver unit. Broadcast transmissions are minimized in favor of unicast messages. The authorization server delivers the IP and MAC addresses of the session-specific OLSs and the subscriber's PC to the remote transceiver units.

Wide area network system providing secure transmission

A bus monitor system comprises eight identical programmable monitor circuits that are each connected to a monitored bus and to a local 16-bit event bus. There are three interfaces to the event bus within each monitor circuit. One interface asserts a predetermined bit pattern on the event bus when match conditions occur between bit patterns on the monitored bus and predetermined bit patterns stored in monitor circuit registers. A second interface asserts a signal on an external pin when bit patterns on the event bus match a predetermined bit pattern stored in a monitor circuit register. A third interface asserts a predetermined bit pattern on the event bus when an external device has asserted a signal on an external pin. Each monitor circuit is capable of reading and asserting any of the bits of the event bus. The event bus is used to enable or disable monitor circuit interfaces. If any asserted bit on the event bus matches a corresponding bit of one of the predetermined bit patterns stored in the interface enable and disable registers, that interface will be enabled or disabled, respectively. The event bus gives the monitor system the ability to simultaneously monitor for multiple bit patterns on the monitored bus, and to monitor for a sequence of bit patterns by having one monitor circuit trigger another.

Bus monitor system

Two major Forth extensions provide high-level support for building rapid prototypes for systems. These extensions form distinct language vocabularies available in the Forth environment. One is a Finite State Machine Language, named FSML, and the other is an object oriented language, named 200L. Using these extension and the inherent expandability of the Forth language, a prototype can be rapidly created. The modeling method requires four steps. First, using 200L, the system is described as a set of objects. At least one of the objects must be a controlling object and so identified. Second, using FSML, the controlling object is described as a finite state machine. Third, the system's operation is expressed as a collection of one or more finite state machines. Each finite state machine type is defined with a unique machine type name. Any number of instances of a finite state machine type can be dynamically created at execution time. Fourth, communication is allowed between the finite state machines.

Method for rapid development of software systems

Air freight pallet

A shipping container especially adapted for air freight movement of perishable goods in which separable base, wall members, and cover portions are assembled and disassembled on site. The base is formed of a rigid preferably plastic material and is of a general planar configuration with a peripheral groove for receipt of wall members in turn preferably formed from corrugated cardboard and the like and which define lower peripheral edges such that the separate wall members may be forced into the grooves to construct a compartment for the receipt of the material being shipped. Upon reaching the destination, the assembly may be easily dismantled and the corrugated cardboard wall members either discarded or returned back to the point of origin along with a plurality of stacked rigid bases.

Reusable air freight container assembly

An arrangement for connecting an array of individual electronic elements into a readily expandable matrix. The arrangement comprises a plurality of matrix slices with each slice including a set number of electronic elements as well as a row and a column buffer. The electronic elements of each matrix slice are diagonally connected to the elements of the adjacent matrix slice.

Expandable electronic matrix

A formatted data message for conveying control information from the peripheral processor of one telecommunications switching system to the peripheral processor of at least one other telecommunications switching system is provided. The data message format comprises a first control work including a plurality of control bits, a data bit and a parity bit for the first control word and a plurality of data words, each data word including a parity bit. The data words contain control information to be conveyed to the receiving peripheral processor. A parity word is included which provides parity for an associated plurality of the preceding data and control words.

Data format arrangement for communication between the peripheral

In a telecommunications switching system, a thick film digital span conversion circuit is connected between a digital span and a switching network of the switching system. The circuit converts data, which is encoded for digital span use, to TTL logic coding for use by the switching network. The telecommunications switching system also provides for duplicated data transmission through the switching network. Duplicated conversion circuits are employed in an active/standby configuration under CPU control. The present circuit is relatively small in size and has minimal power consumption.

Digital span conversion circuit

A receive data reformatter for a telecommunications switching system is shown for disassembling a data message to a plurality of 8-bit data bytes. The receive data reformatter is comprised of a parallel to serial converter which receives the data message one byte at a time which it subsequently outputs serially. A horizontal parity check circuit receives the serial data and is arranged to output an error signal when an error in parity is detected. A serial to parallel converter, connected to the serial output of the parallel to serial converter, receives the serial data and assembles the serial data into parallel form. A write buffer connected to the serial to parallel converter receives the assembled parallel data when eight data bits have been accumulated in the serial to parallel converter. The thus formed data byte is output to a peripheral processor of the telecommunications switching system.

Remote data link receive data reformatter

A transmit data formatter is provided for assembling a plurality of 8-bit data bytes into a data message containing a plurality of message bytes. The transmit data formatter includes a receive buffer which receives a data byte from a peripheral processor. A parallel to serial converter receives the data byte from the receive buffer and outputs the data byte serially. A serial to parallel converter receives the serial data byte and assembles the data byte into a partial message byte when seven data bits have been received. A horizontal parity generator connected to the parallel to serial converter develops a horizontal parity bit which is appended to the seven data bits forming a message byte.

Remote data link transmit data formatter

The present invention provides for synchronizing signals transmitted to two duplex copies of hardware from a common source. Signals sent from the source to the duplex copies of hardware may arrive asynchronously at the two copies and require synchronization. In addition, the duplex hardware may be validly operated in the simplex mode of operation, which requires no synchronization of the two hardware copies.

Circuit for duplex synchronization of asynchronous signals

In a PCM telecommunications switching system, an arrangement for deriving a clock signal from incoming PCM data of a digital span is shown. This derived clock signal is synchronized and continuously locked to the incoming PCM data of the digital span. The present digital phase locking arrangement cyclically adjusts the derive clock signal so that on the average synchronism is maintained.

Digital phase locking arrangement for synchronizing digital span data

This circuit provides for synchronizing the internal clocks of at least two central processing unit process controllers. In order to synchronize the internal clocks of these central processing units (CPUs), the CPUs periodically execute a predetermined set of operating instructions which cause their internal clocks to coincide. This synchronization function is dynamic in that it is continually performed in an on-line fashion while the processors are performing their telecommunication process control function.

Duplex central processing unit synchronization circuit

An address sequencer and memory arrangement is shown for transferring data in the form of message bytes to and from a plurality of digital data links. The address sequencer and memory arrangement includes a memory circuit having a plurality of memory location areas associated with each of the plurality of digital data links. A counter circuit connected to the memory circuit is loaded with a preset count by a link processor complex. The counter increments and outputs to the memory circuit addresses which sequentially access each of the memory location areas, transferring each message byte to a data link output buffer for transmission over a respective one of the plurality of digital data links. Alternatively, the counter addresses sequentially each memory location area transferring a message byte to each memory location area from each of the plurality of digital data links via a data link input buffer.

Remote data link address sequencer and a memory arrangement for

In a telecommunications switching system, a thick film digital span conversion circuit is connected between a digital span and a switching network of the switching system. The circuit converts data, which is encoded for digital span use, to TTL logic coding for use by the switching network. The telecommunications switching system provides for duplicated data transmission through the switching network. Duplicated conversion circuits are employed in an active/standby configuration under CPU control. On-line replacement of a fault conversion circuit may be performed without a switching service interruption.

Growing community of inventors

Phoenix, AZ, United States of America

Thomas J Perry