Microsoft Technology Licensing, LLC

Thomas J Ootjers

Jeffrey Che Fuller

Bruce Lee Worthington

David Matthew Kruse

Mathew George

Ramanathan Ganapathy

Dynamic thread count optimizations include determining: (i) a detected quantity of unassigned IO requests; (ii) a quantity of IO requests currently in process; (iii) a thread pipeline value required to fill a thread's pipeline capacity and based on ratio of (a) an IO duration time from when an IO request is issued until a corresponding IO completion is received and (b) an IO processing time from when an IO request is assigned to a thread until it is issued; and (v) an ideal thread quantity based on a ratio of (a) the quantity of IO requests to be processed and (b) the thread pipeline value. Said optimizations also include dynamically activating new threads whenever a quantity of active threads is determined to be less than the ideal thread quantity.

Dynamic thread count optimizations

A method and system for managing remote file system requests between client and server redirectors where a set of data request packets may be aggregated and/or ordered at a server based on hint information from a client.

Aggregation and re-ordering of input/output requests for better performance in remote file systems

A cache controller in a computer system is configured to manage a cache such that the use of bus bandwidth is reduced. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.

Non-blocking data transfer via memory cache manipulation

A cache controller in a computer system is configured to manage a cache. The cache controller receives commands from a processor. In response, a cache mapping maintaining information for each block in the cache is modified. The cache mapping may include an address, a dirty bit, a zero bit, and a priority for each cache block. The address indicates an address in main memory for which the cache block caches data. The dirty bit indicates whether the data in the cache block is consistent with data in main memory at the address. The zero bit indicates whether data at the address should be read as a default value, and the priority specifies a priority for evicting the cache block. By manipulating this mapping information, commands such as move, copy swap, zero, deprioritize and deactivate may be implemented.

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Kirkland, WA, United States of America

Thomas J Ootjers