Intel Corporation

Thomas J Mozdzen

Harry Muljono

Lawrence T Clark

Peter D MacWilliams

Larry E Mosley

Christopher P McAllister

Orlando Davila

An apparatus includes a first fuse, a second fuse and a circuit. The circuit uses the first fuse to indicate a stored value for a fuse memory location, and in response to the fuse memory location being rewritten, the circuit uses the second fuse to indicate the stored value for the fuse memory location.

Rewritable fuse memory

Briefly, in accordance with one embodiment of the invention, an integrated circuit includes: an output buffer. The output buffer includes semiconductor devices coupled to provide circuit configurations. The output buffer is adapted to couple to separate voltage supply voltage level ports and is further adapted to switch between the circuit configurations. The respective circuit configurations are respectively specifically adapted for interoperating with other integrated circuit chips, the respective threshold voltage levels of the semiconductor devices of different other integrated circuit chips being different.

Output buffer for high and low voltage bus

An integrated circuit device package. A substrate includes a first terminal coupled to the substrate. First and second conductive traces are formed on the substrate and are electrically coupled to the first terminal wherein the first conductive trace is provided to electrically couple a first bondwire to the first terminal and the second conductive trace is provided to electrically couple the second bondwire to the first terminal.

Interleaving a bondwire between two bondwires coupled to a same terminal

A boundary scan cell for testing an integrated circuit comprises an output buffer for driving a pad of the integrated circuit, a capture register coupled to the pad through the output buffer, and an input buffer drives a signal present at the pad to a node coupled to core logic of the IC. A first multiplexer is included to have a first input coupled to the node, a second input coupled to data of a previous scan stage, and an output coupled to the capture register. Logic circuitry selectively enables/disables the input and output buffers responsive to first and second control signals such that the I/O buffers can drive the pad and, at the same time, drive the input buffer, the output of which is coupled to the input of the capture register.

JTAG boundary scan cell with enhanced testability feature

A method and apparatus for communicating signals between a source synchronous component and a non-source synchronous component of a system is described. The present invention provides a strobe signal from the source synchronous component that is delayed and used to latch data received from a non-source synchronous component. The amount of delay provided is determined based on the timing of data request cycles to the non-source synchronous component. Thus, the present invention allows data to be received by a source synchronous component from a component that does not generate a strobe signal used for latching received data that would be generated by a source synchronous component.

Method and apparatus for capturing data from a non-source synchronous component in a source synchronous environment

An integrated circuit device package. The package includes a package substrate having a conductive bondring disposed thereon. A via is electrically coupled to the bondring. A conductive bondring extension is also disposed on the package substrate. The bondring extension is electrically coupled to the bondring and the via and extends away from the bondring and the via.

Method and apparatus for connecting a bondwire to a bondring near a via

A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the circuit comprising a plurality of data drivers and a plurality of delayed I/O clock generators, wherein the I/O clock generators generate delayed I/O clocks signals that follow the I/O clock signal by a phase multiple of the core clock signal. The integrated circuit outputs data through output nodes that are synchronized with I/O clock signal. By outputting data signals in the I/O clock domain and using the delayed I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals are valid before the external component latches the data. A set of data signals and a delayed I/O clock are generated from similar drivers to further ensure that the data signal is valid before the external component latches the data.

Method for eliminating multiple output switching timing skews in a

A bus pattern for an integrated circuit package. The package has a first conductive bus and a second conductive bus that are located on a bond shelf. The first conductive bus has a plurality of interconnected tab portions that are separated by a plurality of non-conductive slots. The second conductive bus has a plurality of interconnected tab portions that are located within the non-conductive slots of the first bus. The tab portions of each bus are wire bonded to a plurality of die pads located on an integrated circuit that is mounted to the package.

Method and apparatus to reduce cavity size and the bondwire length in

A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the integrated circuit comprising a plurality of data drivers and a plurality of external I/O clock generators, wherein the external I/O clock generators generate external I/O clocks signals using circuitry identical to the data drivers except for a slight increase in the channel length of the pre-driver and driver transistors. These transistors control the transition time of the external I/O clock output node. By outputting data signals in the I/O clock domain and using the external I/O clock signals to synchronize transmission with external components, the integrated circuit ensures that the data signals transition before the transitions of the external I/O clock signals regardless of process induced signal variations. A set of data signals and a delayed I/O clock are generated from similar drivers to further ensure that the data signals are asserted before the transition of the external I/O clock signal.

Method for eliminating process variation timing skews in a source

A source synchronous computer system to ensure the capturing of signals transmitted from a first component to a second component. An integrated circuit operating on a core clock signal and an I/O clock signal, the integrated circuit comprising a plurality of data drivers, an external I/O clock generator for transmitting the I/O clock signal, and an inverting external I/O clock generator for transmitting the compliment of the I/O clock signal, wherein the data drivers output data synchronous to the I/O clocks and both transmitted clock signals are combined in a receiving component to form a third clock. The receiving component capturing the outputted data synchronous to the third clock. By outputting data signals in the I/O clock domain and using the combination of the transmitted clock signals to synchronize transmission between external components, the computer system ensures that various output conditions that shift the rising or falling edge of a synchronizing clock are adjusted for by the receiving component generating a third clock that selects the later of the rising or falling clock edge between the transmitted clock signals. A set of data signals, the transmitted I/O clock signal, and the transmitted compliment I/O clock signal are generated from similar drivers and share a common power supply plane to further ensure that the data signals are asserted before the clocking edge of the generated third clock.

Method for eliminating transition direction sensitive timing skews in a

A method and apparatus for placing a microprocessor in and out of a reduced power consumption state utilizing system interrupts in a computer system. The method of the present invention intercepts instructions being executed by the processor before placing the processor in a reduced power consumption state. On a request for the processor to exit the reduced power consumption state, the method of the present inventions allows the processor to execute pre-determined resume instructions to wait out any voltage level fluctuations in the processor as it exits the reduced power consumption state, before allowing the processor to continue execution of the instructions intercepted prior to placing the processor in the reduced power consumption state.

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Gilbert, AZ, United States of America

Thomas J Mozdzen