Thinking Machines Corporation

Thomas J Moser

Edward C Parish

David Potter

William A Nesheim

David L Satterfield

James P Tardiff

Sharon E Gillett

Robert A Doolittle

A data transfer arrangement for use in a data processing system comprising a processing array and at least one input/output unit and a host for issuing commands, including data transfer commands, to both the processing array and the input/output unit. The processing array and input/output unit include interfaces are interconnected by a bus and comprise an information transfer means, a control transfer means including a cycle identifier transfer means, and a transfer control means. The information transfer means transmits and receives information signals, including arbitration, target select and data signals, over information transfer lines of the bus. The cycle identifier transfer means transmits and receives cycle identifier signals over cycle identifier lines of the bus. The transfer control means is connected to the information transfer means and the control transfer means and enables a data transfer in a plurality of phases, including an arbitration phase, a selection phase and a data transfer phase. In particular, the control transfer means enables the information transfer means to transfer over the information transfer lines (i) arbitration signals in response to receipt of cycle identifier signals identifying an arbitration operation by the cycle identifier transfer means to thereby engage in an arbitration operation; (ii) target select signals during a target select phase in response to results of the arbitration operation to thereby engage in a target select operation, and (iii) data signals in response to results of the target select operation.

System for transferring blocks of data among diverse units having cycle

A high performance communications interface device for connecting a high speed computer to a high performance communications bus. The high performance communications interface device includes a high performance communications interface device processor, a source interface, a destination interface and at least one I/O processor which controls the transfer of data to the high speed computer from the high performance communications bus and from the high speed computer to the high performance communications bus.

High performance communications interface for multiplexing a plurality

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Lowell, MA, United States of America

Thomas J Moser