Analog Devices,inc.

Thomas J Meany

Paul P Wright

Shaun Bradley

Adrian Sherry

John O'Dowd

Andreas Callanan

Tomas Tansley

John P Healy

Paul Maher

Patrick R Hickey

Kieran Berney

Automatic power saving for decreasing power demand during a power interruption while maintaining the appearance of full operation of a signal processor including predefined power consuming circuits, a communications interface, and a state machine includes sensing when a power supply interruption has occurred, providing a clock signal, halting the clock signal to the predefined power consuming circuits during a power interruption; and continuing to provide a clock signal to a communications interface regardless of a sensed interruption for maintaining the appearance of normal operations during the sensed interruption.

Automatic power saving system and method for power interuptions

A circuit die to circuit die interface system includes a first circuit die with a first circuit having a first default signal, at least a second circuit die with a second circuit having a second default signal; and a logic circuit disposed on one of the first and second circuit dies and enabled by a default signal from all but one of the circuits to transmit a communication signal from the remaining circuit.

Circuit die to circuit die interface system

An input biasing system for accommodating a floating power supply to the range of an input signal includes input terminals for receiving a input signal and a biasing circuit including a first impedance connected between one of the input terminals and a floating power supply and a second impedance connected between another of the input terminals and the ground of the floating power supply for bracketing the floating power supply about the input signal.

Input biasing system for bracketing a floating power supply about an input signal

An interface error monitor system for monitoring data exchanged between a controller and a data converter over an interface includes a multi-stage linear feedback shifter register associated with the data converter for generating a pseudo random number sequence; a signature generating circuit responsive to data exchanged between the controller and data converter for altering the pseudo random number sequence generated by the linear feedback shifter register to create a signature of the data.

Interface error monitor system and method

A reduced chop rate analog to digital converter technique including selectively weighting input samples to a digital filter, alternately inverting the polarity of an input error into positive and negative error components; and generating the positive and negative error components in a plurality of time response intervals of the digital filter in which the sum of the weights of the positive and negative error components are substantially equal.

Reduced chop rate analog to digital converter system and method

A multi-channel analog to digital converter which facilitates calibration of the analog to digital converter and respective input channels to the analog to digital converter, and a method for calibrating the analog to digital converter. A multi-channel ADC () comprising an ADC circuit () for converting analog signals received on input channels CHto CHN to digital output signals comprises a primary offset storing register () and a primary gain storing register () for storing respective primary offset and gain correction codes which are applied to the digital output signals in a primary correcting circuit () for correcting for the offset and gain errors introduced by the ADC circuit (). A plurality of secondary offset storing registers () and a plurality of secondary gain storing registers () store respective secondary offset and gain correction codes which are applied to the digital output signals in a secondary correcting circuit () for correcting for offset and gain errors introduced by corresponding ones of the input channels CHto CHN.

MULTI-CHANNEL ANALOG TO DIGITAL CONVERTER WHICH FACILITATES CALIBRATION OF THE ANALOG TO DIGITAL CONVERTER AND RESPECTIVE INPUT CHANNELS TO THE ANALOG TO DIGITAL CONVERTER, AND A METHOD FOR CALIBRATING THE ANALOG TO DIGITAL CONVERTER

A circuit used for testing an integrated circuit including a chop circuit. A source of a test signal coupled to a first pair of pins of the integrated circuit. A test signal measuring device to measure the test signal coupled to a second pair of pins of the integrated circuit. A chop circuit controller produces a control signal and for feeding such control to the chop circuit and the test signal measuring device. In response to the control signal, the chop circuit couples the first pair of pins to the second pair of pins with a first polarity during a first period of time and couples the first pair of pins to the second pair of pins with an opposite polarity during a second period of time.

Circuit for testing an integrated circuit

A clock oscillator having a pair of pins adapted for coupling to an external crystal, a first one of such pair of pins being adapted for coupling to an external clock. A switch, formed on the chip, is provided for electrically decoupling the crystal excitation circuit from one of the pair of pins in response to a control signal. In accordance with one embodiment of the invention, the switch is disposed between the output of a crystal excitation circuit and the second one of the pair of output pins and, in another embodiment, the switch is placed in circuit between the input to the crystal excitation circuit and the first one of the pair of pins. In each of these embodiments, when the switch is in a first condition, clock pulses are prevented from being coupled to the second one of the output pins, either: by preventing the external clock from feeding the input to the crystal excitation circuit; or, by preventing the output of the crystal excitation circuit from feeding the second one of the pair of pins. With such an arrangement, when the external clock is used and fed to the first one of the pair of pins, clock pulses are electrically prevented from appearing at the second one of the pair of pins. Therefore, current will not flow from the crystal excitation circuit into any stray capacitance at the second one of the pins.

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Limerick, Ireland

Thomas J Meany