Bae Systems Information and Electronic Systems Integration Inc.

Ovonyx Inc.

Thomas J McIntyre

Keith K Sturcken

John C Rodgers

Andrew T S Pomerene

John D Davis

Tushar K Shah

Peter W Spreen

Jason F Ross

Andrew T Pomerene

Timothy J Conway

Matthew A Gregory

Charles N Alcorn

Christy A Hagerty

Steve Hudgens

Chi-Hua Yang

Scott K Arnold

A method for verifying stitching accuracy of a stitched chip on a wafer is disclosed. Initially, a set of test structures are inserted within a reticle layout. An exposure program is executed to control a photolithography equipment having a stepper to perform multiple exposures of the reticle on a wafer to generate a stitched chip on the wafer. Electrical measurements are then performed on the test structures at actual stitch boundaries of the stitched chip to evaluate stitching accuracy of the stitched chip.

Method and apparatus for verifying stitching accuracy of stitched chips on a wafer

A method for fabricating a metal-insulator-metal capacitor (MIMCap) is disclosed. A first metal layer is provided on top of an oxide layer. A nitride layer is then deposited on the first metal layer. The nitride layer and the first metal layer are etched to form a MIMCap metal layer. The gaps among the MIMCap metal layer are filled with a plasma oxide, and the excess plasma oxide is polished using the nitride layer a polish stop. After removing the nitride layer, a dielectric layer and a second metal layer are deposited on the MIMCap metal layer. Finally, the dielectric layer and the second metal layer are etched to form a set of MIMCap structures.

Method for fabricating a metal-insulator-metal capacitor

A method for fabricating an electronic device package having a column grid array is disclosed. A column grid array package includes a substrate, an integrated circuit located on a first side of the substrate, and a set of solder columns located on a second side of the substrate. The column grid array package also includes multiple two-tab electronic devices located on the second side of the substrate. The heights of the two-tab electronic devices are substantially identical to the heights of the solder columns.

Method for fabricating solder columns for a column grid array package

An apparatus for providing thermal management on high-power integrated circuit devices is disclosed. Initially, contacts to active devices are formed. Phase change materials are then applied over potential hot spots that can be formed by the active devices. A layer of high-thermally conductive materials is deposited over the phase change materials. The layer of high-thermally conductive materials and the phase change materials are subsequently etched according to a pattern. A layer of passivation conductive vias is subsequently applied to the phase change materials to complete the formation of phase change heatsinks.

Method and apparatus for providing thermal management on high-power integrated circuit devices

A system is provided to aid in laying out circuits on a semiconductor wafer, in which a wafer map is automatically generated when entering chip sizes, arrangements and other enterable factors, with a goal to maximize yield probability. The subject system accommodates different chip types and arrangements within a wafer map and addresses edge exclusion, utilization of chiplets and accommodation of different centering techniques, including a variety of ways of measuring offsets, while outputting a display of replicated circuits on the wafer as well as chip count and density, utilizing a portable, tailorable, extendable PC-based program featuring an easy-to-use graphical interface. The software application provides a user with different graphical views customized for different process areas, such as lithography and dicing, with the application being useful for any semiconductor manufacturing facility, foundry or similar industry that needs to generate wafer maps automatically to maximize yield probability.

Method and apparatus for generating a wafer map

A method and system of forming vertical optical interconnects in optical integrated circuits is disclosed. The method includes forming a first optical transmission layer over a substrate. A first cladding layer is then formed on the first optical transmission layer and portions of the first cladding layer removed to form an angled sidewall in the first cladding layer. An optical interconnect layer is formed on the angled sidewall of the first cladding layer and on an exposed portion of the first optical transmission layer.

Method of forming interlayer connections in integrated optical circuits, and devices formed using same

An integrated photonic device having a vertical optical connection between vertically oriented waveguides and a process for making the same is disclosed. A first waveguide is patterned and etched onto an underlying substrate. A cladding layer is placed over the waveguide and substrate. The cladding layer is coated with a photoresist, and then patterned with holes that are slightly offset from the underlying waveguide. The holes are implanted with nitrogen doses at an angle. The nitrogen doses form an angled implantation of SiON. The material change and accompanying index of refraction change due to the angled implantation optically couples the underlying waveguide with an outside surface of the cladding layer. A second waveguide or circuit can then be patterned on the outer surface of the cladding and connected to the angled implantation and underlying waveguide. Multiple layers of waveguides or circuitry can be connected to each other in this manner.

Integrated photonic circuits with vertical connections

The semiconductor device comprising a chalcogenide phase change material. The chalcogenide material being programmed from one resistance state to another resistance state by applying a programming current to a resistor which is in thermal contact with the chalcogenide material. The semiconductor device may be used as memory element or as a programmable fuse.

Programmable resistance memory element with indirect heating

For those optical waveguides that require the deposition of a thick film and a high-temperature anneal to create an appropriate waveguide medium, wafer warping, bowing or dishing is reduced or eliminated by depositing a film of the same thickness on the backside of the wafer so as to relieve film stress during the deposition and annealing process. In one embodiment the waveguide medium is silicon oxynitride, although other depositable thick films may be utilized in place of the silicon oxynitride.

Backside deposition for relieving stress and decreasing warping in optical waveguide production

A thermoelectric microactuator on a substrate includes a first temperature control element having a first surface bonded to the substrate and having a second surface. A first electrically nonconductive layer has a first surface bonded to the second surface of the first temperature control element and has a second surface. An actuator arm includes a first region bonded to the second surface of the first nonconductive layer and includes a flexure contiguously extending from the first region to an end cantilevered beyond the first nonconductive layer and forming an axis at the junction of the flexure and the first region. The first temperature control element controls the temperature of the actuator arm to thereby deflect the flexure about the axis.

Thermoelectric microactuator

A method for manufacturing a programmable chalcogenide fuse within a semiconductor device is disclosed. A resistor is initially formed on a substrate. Then, a chalcogenide fuse is formed on top of the resistor. Finally, a conductive layer is deposited on top of the chalcogenide fuse for providing electrical conduction to the chalcogenide fuse.

Method for manufacturing a programmable chalcogenide fuse within a semiconductor device

A method for manufacturing a thermoelectric cooling mechanism for an integrated circuit is disclosed. Initially, electric circuits are formed on one side of a wafer. Subsequently, thermoelectric cooling devices are formed on an opposite side of the same wafer. Specifically, the thermoelectric cooling devices are formed by depositing a first conductive layer, depositing a layer of Peltier material on top of the first conductive layer, building a set of N regions and P regions within the Peltier material layer, and depositing a second conductive layer on top of the Peltier material layer.

Integrated circuit device having a built-in thermoelectric cooling mechanism

An integrated circuit device having a built-in thermoelectric cooling mechanism is disclosed. The integrated circuit device includes a package and a substrate. Contained within the package, the substrate has a front side and a back side. Electric circuits are fabricated on the front side of the substrate, and multiple thermoelectric cooling devices are fabricated on the back side of the same substrate. The thermoelectric cooling devices are utilized to dissipate heat generated by the electric circuits to the package.

Growing community of inventors

Nokesville, VA, United States of America

Thomas J McIntyre