Freescale Semiconductor,inc.

Thomas J Kropewnicki

Kurt H Junker

Paul Grudowski

Ritwik Chatterjee

Andrew G Nagy

A method for forming a TSV layout reduces recessing in a silicon nitride layer caused by forming the TSV through a silicon nitride layer having an intrinsic tensile stress or neutral stress. In one embodiment, the method includes compensating for the tensile stressed silicon nitride layer by either moving the TSV location to an area of intrinsic tensile stress, or by substituting a compressively stressed silicon nitride layer in the area of the TSV. The compressively stressed silicon nitride layer experiences less recessing during a TSV etch process than a silicon nitride layer under tensile stress. The smaller recesses are more readily filled when a dielectric liner is applied to the sidewalls of the TSV, reducing the possibility of voids being formed. Also, the smaller recesses require smaller exclusion zones, resulting in less surface area of an integrated circuit being used for the TSVs, as well as greater reliability and improved yields.

Method for forming a through silicon via layout

A method for making a semiconductor device is provided, comprising (a) providing a semiconductor structure comprising a first gate electrode (); (b) forming a first set of organic spacers () adjacent to said first electrode; (c) depositing a first photo mask () over the structure; and (d) simultaneously removing the first set of organic spacers and the first photo mask.

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Austin, TX, United States of America

Thomas J Kropewnicki