Dell USA L P

Dell Products Inc.

Other

Thomas J Kocis

Jacob Cherian

Orin Michael Ozias

Pearce R Jones

John P Busch

Mark B Penniman

Michael D Durkin

Dan E Swindler

Thomas Shu

Darius D Gaskins

Robert H Garrett

Deepak N Swamy

Philip Dale Chidester

Mark A Larson

Charles W Morrison

Derek Westmoreland

Anthony K Patterson

Stephen K Smith

A system and method for managing the multipath failover protocol of a storage area network that includes storage systems that include multiple ports and multiple storage controllers. A number of available storage paths between each server and each storage unit of the storage system are identified. A storage path is selected. In the event that the storage path becomes inoperable, an alternate storage path is selected in replacement of the inoperable storage path. The alternate storage path will be selected so that it does not include a storage controller that was part of the inoperable storage path.

System and method for a failover protocol in storage area network controllers

A system and method for correlating the command queue depth of the servers of a storage area network to the command queue depth of the storage controllers of the computer network are provided. For each storage controller, the servers are identified that have logical ownership of the logical storage units managed by each respective storage controller. For each storage controller, the execution throttle levels for those servers that have logical ownership over logical storage units of the storage controller are verified according to rules governing the command throughput of the servers and the storage controllers. If, for any of the storage controllers of the network, the summed execution throttle level exceeds the command queue depth of the storage controller, the execution throttle level of one or more of the servers of the network is adjusted to insure that the potential command throughput of the servers of the network conforms to the standards established for governing the relation of command throughput between servers and storage controllers.

System and method for matching storage device queue depth to server command queue depth

A system and method are provided for adding an internal RAID controller. The system and method includes a plurality of hard disk drives storing data. Hard disk drive bays receive the hard disk drives. A modified hard disk drive bay accepts a RAID controller. The user inserts the RAID controller into the modified hard disk drive bay allowing data transfer between the hard disk drives, the RAID controller, and the motherboard of the computer on two interface loops. One interface loop, the control loop, provides an interface between the loop controller on the motherboard and the RAID controller. The other interface loop, the storage loop, provides an interface between the RAID controller, the hard disk drives, and any external hard disk drives. The RAID controller communicates with the motherboard allowing RAID functionality among the hard disk drives.

System and method for adding an internal RAID controller

Method and apparatus for transitioning an electronic device operable in a reduced power consumption mode from the reduced power consumption mode to a full power mode immediately before a user attempts to operate the device is disclosed. A hand held intelligent data entry unit (IDEU) of the present invention is provided with a noncontact sensor for detecting the prepense of a user's hand within an predefined actuation region of the IDEU while the IDEU is operating in a low power consumption mode. Responsive such detection, the sensor generates a wake up signal to a microprocessor of the IDEU for causing the IDEU to transition from the low power consumption mode to a full power mode.

Capacitive wake-up mechanism for hand held data entry unit

A docking station structure is used to operatively connect a notebook computer to desktop computer peripheral devices. The docking station has an internal receiving chamber into which the portable computer may be manually inserted, an electrical connector positioned within the receiving chamber, a travel plate movably carried within the receiving chamber, a motorized drive system operative to drive the travel plate toward and away from the electrical connector, and a latch structure carried by the travel plate for movement therewith. With the travel plate in a wait position thereof, the portable computer is rearwardly inserted into the receiving chamber. In response to such insertion, the latch structure automatically locks the computer to the travel plate, and the drive system rearwardly moves the travel plate to mate the electrical connector with a corresponding connector on the computer, thereby operatively linking the computer to the peripheral devices. To remove the computer, the drive system is operated to forwardly move the drive plate and the computer to an ejection position in which the computer and docking station electrical connector structures are disconnected from one another, and the computer is unlocked from the travel plate. Upon insertion of the computer into the docking station opposite side portions of the computer are slidingly received in docking station track indentations operative to maintain the computer in a precisely aligned relationship with the docking station electrical connector during driven movement of the computer.

Motorized portable computer/expansion chassis docking system

A battery powered computer system has a drive motor and a motor speed control. The motor speed control receives electrical power from an unregulated source in the computer, such as a battery. The motor speed control may include a pulse width modulator which pulsates received electric potential for use by the drive motor. The motor speed control may also contain control circuitry which controls the supply of pulsated electrical power to the drive motor. The control circuitry may also supply the pulsated voltage to the drive motor in duty cycles based on feedback from the drive motor to the control circuitry. For large voltage power supplies, the motor controller may have a voltage limiter to limit the maximum voltage from the power supply to the pulse width modulator.

System and method for controlling a computer drive motor

A telephonic customer support utility for providing diagnostic support of a customer computer including encoding an operational status of a customer's computer to produce audible tones on a speaker corresponding to the encoded status for transmission on a standard telephone line via a standard telephone of the encoded operational status to a remote support computer, the remote support computer having a receiver electrically connected to receive the tones transmitted on the telephone line. The received tones are decoded by a decoder of the remote support computer to determine the operational status of the customer's computer, which status is displayed on a display of the remote support computer for analysis by a customer support technicians.

Telephone customer support utility

A ceramic package for an integrated circuit (IC) and a method of manufacturing the ceramic package. The package comprises: (1) a ceramic body having opposing substantially planar first and second surfaces thereon, a cavity in the body and a plurality of vias passing through the body and intercepting the first and second surfaces, (2) an integral IC located within the cavity, (3) a plurality of electrical conductors located on the surfaces, passing through the plurality of vias and coupled to the IC, the plurality of conductors adapted to allow communication of electrical signals through the body and with the IC and (4) first and second electrical connectors located on the first and second surfaces, respectively, the first electrical connector allowing an optional IC to be removably mounted to the package and coupled to the plurality of electrical conductors, the second electrical connector allowing the package to be mounted to a supporting circuit board, the package thereby allowing the integral and optional ICs to communicate the electrical signals therebetween and with the circuit board.

Ceramic integrated circuit package with optional IC removably mounted

A DRAM circuit is disclosed with circuitry for disabling data output drivers to prevent bus contention during system power-up. The circuitry includes a counter for counting RAS (or CAS) signals, and for disabling the output data drivers until 7 RAS (or CAS) signals are counted. The output of the counter (called Keep Off) connects to each of the tri-state buffer output drivers, through an AND gate. Other inputs to the AND gate may include an output signal Pwrup from a voltage detection circuit, and other enable signals. The counter uses the RAS signals as a clock signal to three D flip-flops. The Pwrup signal also is used as a reset to each of the flip-flops. The Q output of the flip-flops are anded together, to produce a signal which is released when the count reaches 111.

Apparatus and method for preventing bus contention during power-up in a

A specially designed metal grounding cap is placed over a metal-plated housing boss upon which a printed circuit board is to be mounted by extending a screw through a hole in the circuit board and tightening the screw into a metal insert previously forced into the free end of the mounting boss. As the screw is tightened into the boss insert, an EMI grounding pad on the underside of the circuit board engages an end wall of the grounding cap and pushes it into forcible engagement with the inner end of the boss. The forcible engagement of the grounding cap end wall causes leg portions of the cap to pivot inwardly and engage portions of the plated boss side wall between the boss insert and the metal plated housing wall from which the boss inwardly projects. The installed grounding cap thus serves as a conductive bridge around plating disturbances on the boss, in the region of the forcibly installed insert therein, to maintain an EMI grounding path from the installed circuit board to the metal plating on the housing wall.

EMI grounding cap structure for use in mounting a printed circuit board

A small computer architecture in which the CPU can receive multiple kinds of interrupt signals, including one kind which is assigned to indicate the occurrence of a keystroke input and another kind which is assigned to indicate the occurrence of a pointing device input. However, the computer does not include any pointing device as such. Instead, the keyboard microprocessor (i.e. a microprocessor other than the CPU) monitors user keystrokes to the computer's keyboard, and: in response to simple keystrokes, or keystroke combinations which include one of the basic chording keys, the keyboard microprocessor sends a keystroke interrupt to the CPU; and in response to keystroke combinations which include an additional chording key, the keyboard microprocessor sends a pointing-device interrupt to the CPU, and provides a data output corresponding to an emulated pointing-device movement.

Computer with pointing device mapped into keyboard

A computer system where memory access is accelerated by automatically incrementing the address at the memory chip inputs, as soon as the minimum hold time has occurred. If the next address actually requested by the CPU does not match this predicted address, then the actual address is driven onto the chip inputs as usual, so essentially no time is lost. However, if the automatically incremented address does match the next actually requested address, then a significant fraction of the chip's required access time has been saved.

Predictive addressing architecture

Disclosed are a circuit and method for providing automatic termination for a small computer systems interface ('SCSI') bus. The circuit resides within a bus controller comprising (1) a control circuit for controlling transmission of data on a bus and for providing an interface between the bus and a computer system for communication of the data therebetween and (2) a first bus port and a second bus port, each of the first and second bus ports permitting a device to be coupled thereto for communication with the control circuit via the bus, the bus controller being at an end of the bus when a single one of the first and second bus ports is coupled to a device and being in a middle of the bus when both the first and second bus ports are coupled to devices. The circuit of the present invention is coupled to the first and second bus ports and is capable of coupling a terminating circuit to the bus as a function of a presence of devices coupled to the first and second bus ports, the bus requiring coupling of the terminating circuit when the bus controller is at the end of the bus.

Circuit for providing automatic SCSI bus termination

A delay line within an integrated circuit and calibrated by an external time period (calibration clock). The speed of devices in the integrated circuit is assessed using the calibration clock, and this speed then controls how many delay cells within the delay line an input must traverse to trigger the delayed output.

Growing community of inventors

Austin, TX, United States of America

Thomas J Kocis