Northrop Grumman Systems Corporation

Thomas J Knight

Narsingh Bahadur Singh

Andre E Berghmans

Brian Paul Wagner

David A Kahler

David J Knuteson

Sean R McLaughlin

Jerry W Hedrick

Michael Edward Aumer

Robert Miles Young

Deborah P Partlow

Michael Rennie

James Halvis

Christopher F Kirby

Jeffrey David Hartman

Michael Manuel Fitelson

Kenneth J Petrosky

Marc Eisenzweig Sherwin

Joseph Terence Smith

Ty Richard McNutt

Alfred Paul Turley

Godfrey Augustine

George M Bates

Jay Michael Gordon

Mark S Usefara

Travis Randall

Paul James Matthews

Pat J Unkefer

Rodolfo A Martinez

A reconfigurable solar array has a plurality of photovoltaic cells and an interconnect circuit including a plurality of switches for interconnecting the photovoltaic cells. A thermostatic feedback control circuit in communication with a temperature sensor is configured to produce a temperature signal that is proportional to a temperature of the photovoltaic cells. The thermostatic feedback control circuit is configured to cause at least one of the switches to change state at a preset temperature that is independent of supply voltage. When the temperature is above the preset temperature, the photovoltaic cells are arranged in a plurality of strings connected in parallel. When the temperature is at or below the preset temperature, at least one photovoltaic cell in each string is disconnected from a respective string and reconnected in series to each other to form a new string connected in parallel to the other strings.

Reconfigurable solar array for stable output voltage over a range of temperatures with high operational efficiency

A stacked interconnect structure includes a first conductive layer, a second conductive layer, and a first dielectric layer disposed between the first and second conductive layers and having an air gap in a portion of the first dielectric layer that separates the first and second conductive layers. A second dielectric layer is parallel to the first conductive layer, a third dielectric layer overlays a portion of the second dielectric layer and contacts two opposing surfaces of the second conductive layer. A first via extends into the air gap of the first dielectric layer, wherein the second conductive layer is separated from the first via by a portion of the third dielectric layer that extends from a given surface of the third dielectric layer to the second dielectric layer, and a second via that extends from the given surface of the third dielectric layer to the second conductive layer.

Stacked interconnect structure and method of making the same

A method is provided of forming an interconnect structure. The method comprises forming a first dielectric layer overlying a first conductive layer, etching a trench opening in the first dielectric layer, depositing a sacrificial material layer in the trench opening, and forming a second conductive layer overlying the sacrificial layer. The method also comprises forming a via to the sacrificial layer, and performing an etch to remove the sacrificial material layer through the via and leave a resultant air gap between the first conductive layer and the second conductive layer decreasing the effective dielectric constant between the first and second conductive layers.

Photo-conducting infrared sensors are provided including a substrate (e.g., silicon) with one or more trenches formed on a first surface. An infrared-reflective film can be deposited directly or indirectly onto and conforming in shape with the first surface of the substrate. A lead chalcogenide film can be deposited directly or indirectly over the top of the infrared-reflective film and conforming in shape with the first surface of the substrate. Accordingly, the infrared-reflective film is directly or indirectly sandwiched between the substrate and the lead chalcogenide film.

Infrared multiplier for photo-conducting sensors

Methods are provided for forming a capacitor. In one embodiment, a method comprises providing an insulator material layer over a substrate, etching at least one via in the insulator material layer and depositing a contact material fill in the at least one via to form a first set of contacts. The method further comprises etching the insulator material layer adjacent at least one contact of the first set of contacts to form at least one void, depositing a dielectric material layer over the at least one void and over the first set of contacts and depositing a contact material fill in the at least void to form a second set of contacts.

Embedded capacitor and method of fabricating the same

The disclosure relates to a high purity 2H-SiC composition and methods for making same. The embodiments represented herein apply to both thin film and bulk growth of 2H-SiC. According to one embodiment, the disclosure relates to doping an underlying substrate or support layer with one or more surfactants to nucleate and grow high purity 2H-SiC. In another embodiment, the disclosure relates to a method for preparing 2H-SiC compositions by nucleating 2H-SiC on another SiC polytype using one or more surfactants. The surfactants can include AlN, Te, Sb and similar compositions. These nucleate SiC into disc form which changes to hexagonal 2H-SiC material.

Method and apparatus for growing high purity 2H-silicon carbide

A high-efficiency lateral multi-junction solar cell (C) includes ultra-low profile planar spectral band splitting micro-optics having a shortpass filter () reflecting desired frequencies of light () to a reflective mirror () combined with spectrally optimized photovoltaic (solar) cells.

Lateral ultra-high efficiency solar cell

A method for growing a SiC-containing film on a Si substrate is disclosed. The SiC-containing film can be formed on a Si substrate by, for example, plasma sputtering, chemical vapor deposition, or atomic layer deposition. The thus-grown SiC-containing film provides an alternative to expensive SiC wafers for growing semiconductor crystals.

Method of producing large area SiC substrates

High-speed silicon CMOS circuits and high-power AlGaN/GaN amplifiers are integrated on the same wafer. A thin layer of high resistivity silicon is bonded on a substrate. Following the bonding, an AlGaN/GaN structure is grown over the bonded silicon layer. A silicon nitride or a silicon oxide layer is then deposited over the AlGaN/GaN structure. Following this, a thin layer of silicon is bonded to the silicon nitride/silicon oxide layer. An area for the fabrication of AlGaN/GaN devices is defined, and the silicon is etched away from those areas. Following this, CMOS devices are fabricated on the silicon layer and AlGaN/GaN devices fabricated on the AlGaN/GaN surface.

Method for integrating silicon CMOS and AlGaN/GaN wideband amplifiers on engineered substrates

Growing community of inventors

Silver Spring, MD, United States of America

Thomas J Knight