Intel Corporation

Other

Rambus Inc.

Thomas J Holman

Andrew V Anderson

Craig Edward Hampel

Richard Maurice Barth

Ely K Tsern

Peter D MacWilliams

Paul G Davis

Donald C Stark

Abhijit Mukun Abhyankar

Patrick F Stolt

Frederick Abbott Ware

James W Alexander

Randy M Bonella

Stanley Steve Kulick

Mark A Heap

John B Halbert

Hiroyuki Sakamoto

David Nguyen

James A Gasbarro

James M Dodd

Michael W Leddige

Kingsum Chow

Daniel J Allen

Mark A Gonzales

Chung Lam

Chung W Lam

Colin Cunningham

According to one embodiment a computer system is disclosed. The computer system includes memory. The memory includes two or more rows, where each row has a plurality of memory devices. The computer system also includes a chipset. The chipset includes a detection/correction circuit to detect single and double symbol errors and correct single symbol errors for each memory row, and markers to maintain a log of errors within each memory row.

Mechanism for adjacent-symbol error correction and detection

A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases. In an embodiment, a set of m bits of a first symbol and a set of m bits of a second symbol from a first set of data for transmission over a channel during a first clock phase are generated. A set of n bits of the first symbol and a set of n bits of the second symbol from a second set of data over a channel are also generated during a second clock phase. Other embodiments are also claimed and/or disclosed.

Method, system, and apparatus for adjacent-symbol error correction and detection code

One or more multi-level NAND flash cells are operated so as to store only single-level data, and these operations achieve an increased level of charge separation between the data states of the single-level operation by requiring a write to both the upper and lower pages, even though only one bit of data is being stored. That is, the second write operation increases the difference in floating gate charge between the erased state and the programmed state of the first write operation without changing the data in the flash memory cell. In one embodiment, a controller instructs the flash memory to perform two write operations for storing a single bit of data in an MLC flash cell. In another embodiment, the flash memory recognizes that a single write operation is directed a high reliability memory area and internally generates the required plurality of programming steps to place at least a predetermined amount of charge on the specified floating gate.

Method and apparatus for high reliability data storage and retrieval operations in multi-level flash cells

A circuit and method for generating an Error Correcting Code (ECC) based on an adjacent symbol codeword that is formed in two clock phases among other techniques are described. In one embodiment, an apparatus is to comprise one or more logics to: generate a plurality of check bits based on a set of data, receive a codeword from a memory and to generate a syndrome based on the codeword, and to detect whether an error exists based on the syndrome. In another embodiment, a logic may classify the error if it exists. In a further embodiment, a logic may correct the error if it exists. Other embodiments are also disclosed.

A memory module includes a memory module controller to be coupled to a system memory controller by a system memory bus and a plurality of memory devices coupled to the memory module controller, where signaling between the memory module controller and one or more of the memory devices is independent of signal loading or operating voltage of the system memory bus.

Memory module having a memory controller to interface with a system bus

For a client seeking network resources from a network site, such as a web page, audio, visual, or other data, where the network site's desired network resources are also provided by mirroring network hosts, measurements are made to determine a communication efficiency between the client and the network site and mirroring network hosts. The client is then directed to communicate with the network site or a mirroring network host according to which had the highest measured communication efficiency with the client. In such fashion, real time adjustments can be made so as to more optimally distribute client network resource requests across all available sources of the desired network resources, and provide for real time load balancing and fail over of disabled hosts.

Apparatus and method for facilitating access to network resources

Methods and apparatus for a memory system using a new memory module architecture are disclosed. In one embodiment, the memory module has two ranks of memory devices, each rank connected to a corresponding one of two 64-bit-wide data registers. The data registers connect to two 64-bit-wide ports of a 128:64 multiplexer/demultiplexer, and a 64-bit-wide data buffer connects to the opposite port of the multiplexer/demultiplexer. A controller synchronizes the operation of the data registers, the multiplexer/demultiplexer, and the data buffer. In an operating environment, the data buffer connects to a memory bus. When a data access is performed, both ranks exchange data signaling with their corresponding data registers during a single data access. At the buffer, the memory bus data transfer occurs in two consecutive clock cycles, one cycle for each rank. This allows the memory bus transfer rate to double for the same memory bus width and memory device speed.

Dual-port buffer-to-memory interface

System and methods for propagating error status over an error checking and correcting (ECC) protected channel. A first device receives data and an error status associated with the data. The first device generates check bits for the data based on a first ECC code and combines the check bits with the data to form one or more code words. The first device sends the code words across the channel where the first device inserts a triple error into a nibble of at least one codeword sent if the error status indicated an uncorrectable error. A second device connected to the channel receives the code words sent across the channel. The second device detects triple errors within a nibble of any code word and any other single error in the code word using a second ECC code, where the second ECC code is the first ECC code with columns for check bits inserted.

Method and apparatus for propagating error status over an ECC protected channel

A system that has a system memory controller and a memory module. The memory module includes a memory module controller coupled to the system memory controller and a plurality of memory devices coupled to the memory module controller.

Memory system including a memory module having a memory module controller interfacing between a system memory controller and memory devices of the memory module

A memory module controller for providing interface between a system memory controller and a plurality of memory devices on a memory module. The memory module includes first interface circuitry and control logic. The first interface circuitry is configured to receive from the system memory controller a first memory transaction in a first format. The control logic is coupled to the first interface circuitry and configured to convert the first memory transaction into a second memory transaction in a second format for the plurality of memory devices. The second format of the second memory transaction is different than the first format of the first memory transaction.

Memory module controller for providing an interface between a system memory controller and a plurality of memory devices on a memory module

A memory module that has a plurality of memory devices and a memory module controller configured to receive a memory transaction from a first memory bus and to control access to the plurality of memory devices.

Memory module having a memory module controller controlling memory transactions for a plurality of memory devices

The present invention is a method and apparatus for tracking a state of a page of a memory device which has at least a dependent bank structure. A page entry table contains attribute entries of the page. An access control circuit generates access information and a command in response to a memory access. A tracking circuit is coupled to the page entry table and the access control circuit to update the attribute entries in the page entry table according to the command and the access information.

Tracking memory page state

According to one embodiment, a method is disclosed. The method includes interleaving a first error correction code with a second error correction code to generate a third error correction code that provides chip-kill capabilities for a memory system.

Method for detecting and correcting failures in a memory system

A memory system comprising an expansion buffer and a memory expansion channel for connecting a large array of memory devices, such as Direct RDRAMs, to a memory controller. The memory devices are partitioned into subsets of memory devices so that each subset is connected to a unique memory channel for sending and receiving data. The expansion buffer and memory expansion channel provide communication with the memory devices via control packets on the expansion bus, where each control packet has a channel identification field to store a channel identifier; and via request packets on the expansion bus, where each request packet is associated with a control packet. The expansion buffer routes a request packet to a unique channel based upon the channel identifier stored in the associated control packet.

Growing community of inventors

Portland, OR, United States of America

Thomas J Holman