International Business Machines Corporation

Thomas J Hartswick

Anthony K Stamper

Jeffrey P Gambino

Zhong-Xiang He

Eric Jeffrey White

Erick G Walton

David C Thomas

Ronald R Uttecht

Richard A Gilmour

John Edward Cronin

Mark Eliot Masters

Carter W Kaanta

Terrance M Wright

Pei-ing P Lee

A semiconductor structure with low resistance conduction paths and methods of manufacture are disclosed. The method includes forming at least one low resistance conduction path on a wafer, and forming an electroplated seed layer in direct contact with the low resistance conduction path.

Semiconductor structures having low resistance paths throughout a wafer

An aspect of the invention includes a method for plating wires on a wafer comprising: forming an array of integrated circuit (IC) chips having a redistribution level; forming a kerf bus, the kerf bus separating each of the IC chips from each other, the kerf bus being connected to an edge of the wafer; forming an array of wires in the redistribution level of each IC chip; electrically connecting at least one wire in the array of wires on each IC chip to the kerf bus; and electroplating the array of IC chips.

Wafer with plated wires and method of fabricating same

In a semiconductor device using fill shape patterns incorporated into wiring levels to increase the planarity of the wiring levels, the fill shapes are aligned from one wiring level to another wiring level to provide lines of sight to lower wiring levels for visual inspection. Also, in accordance with the invention, selected aligned fill shapes are interconnected with vias to form conductive stacks for contacting lower wiring level conductive wires from upper wiring levels in order to perform electrical test probing/diagnostics.

Method of designing and structure for visual and electrical test of semiconductor devices

A method for determining the quality of features of a photoresist pattern, especially for vias and contacts, formed on a semiconductor wafer. A photoresist mask layer having a pattern of openings therein is deposited onto the wafer, and a test region (kerf) of the wafer is marked through the openings in the mask layer. In a preferred embodiment, the mask layer is a photoresist layer, although in alternative embodiments the mask layer could be provided as an insulator mask layer or a metal mask layer. The marking transfers an image of the bottom of the mask layer into the substrate by etching, such as by rastering a focused ion beam over the openings in the mask layer in the presence of an etchant gas. This provides an etched mark in the wafer defined by the passage of the focused ion beam through the mask opening. In alternative embodiments, the marking could be performed by staining or dyeing. Following the marking step, the mask layer is removed from the test region to facilitate an inspection of the wafer for the presence of the marking while leaving the mask layer in place over remaining portions of the wafer.

Method for measuring submicron images

The preferred embodiment of the present invention provides increased conductivity between interlevel interconnection lines. The preferred embodiment uses sidewall spacers on the sides of the interconnection lines to increase the contact area between interconnection lines and interconnect studs. This increase in area improves connection resistance and allows further device scaling without unacceptable decreases in the conductivity of the connection, and without adding significant expense in the fabrication process.

Interconnects using metal spacers and method for forming same

A method and device to monitor integrated temperature in a heat cycle process is disclosed. A monitor wafer, according to one embodiment, comprises a substrate, typically a silicon wafer, having films of two conductive materials of selected electrical resistances, sequentially deposited thereon. Suitable conductive materials react with each other in the presence of heat to yield a layer of a third, non-conductive or less conductive, material at the interface of the two conductive materials. The thickness of each of the films of the two conductive materials is selected such that the entire thickness is not consumed in the formation of the layer of a third material. Following the heat exposure, electrical resistance of the monitor wafer is determined and compared with the monitor wafer's selected pre-heat electrical resistance. The change in electrical resistance is then correlated to temperature by a thermocouple probe on a set of test wafers having the same blanket metal structure as the monitor wafer.

Method and device to monitor integrated temperature in a heat cycle

Interconnects using metal spacers

The present disclosure sets forth an improved integrated circuit in which circuit elements, adjacent to a fuse, are protected by barriers positioned adjacent the fuse. In the improved integrated circuit the barriers are non-frangible, high melting point structures buried in the passivating layer, covering a wiring layer containing a fuse, and are between the fuse and adjacent circuit elements in the wiring layer structures. Also taught is a method of protecting circuit elements adjacent a fuse comprising the steps of depositing an insulating layer on the surface of a semiconductor device having active regions therein, forming a plurality of fuses and circuit elements in said layer, coating said fuses and elements with a second insulating layer, patterning said second insulating layer to form grooves between each of said fuses and any adjacent fuse or circuit element, and depositing a high melting point and non-frangible material in said grooves.

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Underhill, VT, United States of America

Thomas J Hartswick