International Business Machines Corporation

Cadence Design Systems, Inc.

Lockheed Martin Corporation

Thomas J Eckenrode

Steven Lee Gregor

R Dean Adams

Kamran K Zarrineh

David Robert Stauffer

Garrett Stephen Koch

Walter S Richter

Gary S Koch

Jerry L Twoey

Rebecca Stempski McMahon

Rebecca Stempski

Stan W Driggs

Systems and methods are presented for associating time slices of a received signal with previously encountered time slices. A parameter determination component determines at least one parameter for each received time slice. A content addressable memory stores a plurality of parameter values associated with the previously encountered time slices. The content addressable memory is searchable such that the determined at least one parameter for each received time slice can be compared to the stored plurality of parameter values to provide a memory output. An emitter matching component associates a given received time slice with one of a plurality of emitters according to the memory output.

Robust pulse deinterleaving

A microcode programmable built-in-self-test (BIST) circuit and method for testing a multiported memory via multiple ports, either simultaneously or sequentially, as directed by a microcode instruction word. The microcode instruction word contains a plurality of executable subinstructions and one bit of information that controls whether the test operations prescribed in the plurality of subinstructions shall be executed in parallel or in series. The executable subinstructions are dispatched by a primary controller to subcontrollers which perform test operations at each port according to the subinstructions. The microcode programable BIST architecture flexibly facilitates the testing of multiple devices, multiported devices, including multiported memory structures and complex dependent multiported memory structures. The BIST supports in-situ testing of the functionality of the memory at wafer, module, and burn-in, as well as system-level testing.

Programable multi-port memory BIST with compact microcode

A method and system for testing multiported memories, especially when one or more of the ports are not directly accessible without intervening logic. The method and system segregates the multiported memory into at least two portions which are then used for testing the one or more ports which are not directly accessible.

Method and apparatus for testing multi-port memories

A system and methodology for testing memory in an integrated circuit implementing BIST testing to calculate row and column redundancy and enable replacement of a defective row or column of memory cells. The system comprises circuitry for detecting a first single memory cell failure in a row; and, recording the I/O value of the first Single Cell Fail (SCF). A circuit is provided for detecting whether more than one single cell failure has occurred for a tested row, and, in response to detecting a second SCF, comparing recorded I/O value of the subsequent tested row, with the I/O value associated with the first failed memory cell. Upon detection of defective bits, the defective column and row of memory having corresponding defective bits set is replaced.

Two-dimensional redundancy calculation

A built-in self test system () and method for two-dimensional memory redundancy allocation. The built-in self test system is adapted to allocate two redundant columns () and one redundant row () to an embedded memory () as needed to repair single cell failures (SCFs) within the rows () and columns of the memory. The self-test system includes a left-priority encoder (), a right-priority encoder (), and a greater-than-two detector (). The left-priority encoder encodes the location of the first SCF most proximate the most-significant bit of the corresponding word. The right-priority encoder encodes the location of the first SCF most proximate the least-significant bit of the corresponding word. The greater-than-two detector determines whether a word contains more than two SCFs. If the greater-than-two detector detects that a word contains more than two SCFs, the built-in self test system identifies the corresponding row as being a must-fix row, since the number of SCFs exceeds the number of redundant columns.

Built-in self test system and method for two-dimensional memory redundancy allocation

The functionality of a programmable memory built-in self-test (BIST) arrangement for testing an embedded memory structure of an integrated circuit is extended to system level testing to ascertain operability of the system after the integrated circuits and boards including them have been placed in service in larger systems, by generating default test signals which are loaded in an instruction store module when test instructions are not provided from an external tester. This additional utility of the BIST arrangement, increases efficiency of chip space utilization and improves the system level test. Loading of test instructions from an external tester during chip manufacture and/or board assembly is unaffected.

System initialization of microcode-based memory built-in self-test

A finite state machine (FSM) is used to generate, in real time, potentially long sequences of signals which control generation of signals for application to a memory structure during a self-test procedure which is provided in hardware on the same chip with the memory structure. The FSM-based instruction generator requires much less area than is required for storage of a corresponding number of microcode instructions and allows the built-in self-test (BIST) controller to have a modular architecture permitting re-use of hardware designs for the BIST arrangement with consequent reduction of elimination of design costs of the BIST arrangement to accommodate new memory designs. The sequential nature of the operation of a finite state machine as it progresses through a desired sequence of states is particularly well-suited to controlling capture of signals where access to high. speed data transfer circuits cannot otherwise be accommodated.

Programmable memory built-in self-test combining microcode and finite state machine self-test

A History Store Circuit (HSC) is employed with a commercially available FDDI chipset to provide an interface between the PHY layer hardware and a memory system to record symbol stream segments received from the FDDI network. Memory system address and control signals are provided by the HSC. Multiplexor logic is included to support dual-ring network configurations. The HSC provides the electrical interconnection required to interface to the PHY layer hardware so as to allow reception of invalid frames, valid frames, and invalid/valid line state symbol streams from the fiber optic bus. In order to receive such invalid frames and state symbol streams from the fiber optic media, additional logic is provided to allow the user to focus on the segment of network traffic of interest. The HSC includes a Symbol Stream Comparator (SSC) and History Store Triggering Logic (HSTL) to facilitate control of the network traffic segment captured by the HSC. Using this logic, history store capture can be started or stopped based upon receipt of a specific network symbol stream. This allows the user to selectively collect symbol stream data from the network based upon a triggering symbol stream.

FDDI network test adapter history store circuit (HSC)

An apparatus for injecting errors into a FDDI token ring network is disclosed. The error injection scheme operates by fooling a FORMAC into thinking it sent a real frame of data. This is done by using two RAM buffers. The RAM buffer normally accessed by the RBC/DPC becomes a SHADOW RAM during error injection operation. A dummy frame is loaded into the shadow RAM in order to fool the FORMAC. This data is just like the data that would be used if sending a normal frame, with the restriction that it must be shorter than the error injection data. The other buffer, the error injection RAM, contains the error injection frame. The error injection data is sent out to the media by switching a multiplexor. When the FORMAC is done transmitting the data, the multiplexor is switched back to the normal mode. Thus, the FORMAC is unaware of what happened and the token ring remains operational.

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Endicott, NY, United States of America

Thomas J Eckenrode