Analog Devices Global

Stmicroelectronics N.v.

Analog Devices,inc.

University of Limerick

Thomas J Conway

Patrick J Meehan

Donal G O'Sullivan

Jason D Byrne

Christopher Peter Hurrell

William Hunt

Michael Hennessy

Mark T Kelly

Adrian P Brokaw

Michael J Cusack

Aldrick S Limjoco

Aldrick Limjoco

Philip Quinlan

An integrated electronic component assembly can include an electrically-conductive structure comprising two or more electrically-conductive terminals accessible on an exterior of the integrated electronic component assembly, a first component attachment region for a first component within the integrated electronic component assembly, and a second component attachment region for a second component within the integrated electronic component assembly. The integrated electronic component assembly can include an electrically-conductive magnetically-permeable shield coupled to or defined by the electrically-conductive structure, the electrically-conductive magnetically-permeable shield located between the first and second component attachment regions, including a portion extending in a direction out of a plane defined by the first and second component attachment regions, to suppress magnetic coupling between the first and second components.

Vertical magnetic barrier for integrated electronic module and related methods

A circuit and method to filter a signal is provided. The circuit includes a notch filter circuit to receive an input signal and first and second tuning signals and to provide an output signal. The notch filter circuit has an input-output frequency response that includes a stopband region. The stopband region has a center frequency and has an attenuation level that is based at least on a tuning signal. The tunable filter circuit further includes a tuning circuit operable in at least two modes to generate the tuning signal. The at least two modes includes a tuning mode and a filtering mode. The tuning circuit generates the tuning signal such that the attenuation level of the stopband region is greater in the filtering mode than in the tuning mode.

Resonance detection and filtering circuitry

A signal processing apparatus that includes a circuit in which a signal processing function is performed during a first time period, the signal processing apparatus including or being associated with a switch or a filter in a power supply to the signal processing apparatus so as to disconnect the signal processing apparatus from the power supply or to filter the power supply during a second time period that is coincident with at least part of the first time period.

Method of improving noise immunity in a signal processing apparatus, and a signal processing apparatus having improved noise immunity

A switching regulator IC contains both switching regulator circuitry and an inductor and a capacitor connected in parallel to form a resonant circuit having an associated notch filter frequency response arranged such that, when connected to receive the regulated output voltage, the resonant circuit attenuates the ripple component. This is accomplished by matching the resonant notch to the ripple's fundamental frequency, either manually or automatically. In addition, the resonant circuit's inductor and capacitor can act in concert with decoupling capacitors coupled to the load to form a low pass filter which attenuates harmonics of the ripple's fundamental frequency.

Switching regulator with integrated resonant circuit for ripple filtering

A detector system detects values on a storage medium where there is ISI. The symbols are stored as pits in a close hexagonal lattice having u, v, and x dimensions at mutual 60&#xb0; separations from an individual pit. The value for a particular symbol is determined by generating an estimate for the symbol in each of the u, v, and x dimensions. These estimates are used to generate a decision for the symbol as it is at the intersection of these dimensions. Thus a number of 1-dimensional detectors can be used although the platform is two-dimensional with ISI.

Data detector system

A data processing circuit includes a digital data source having an output carrying a sequence of digital signals. A pre-filter is coupled to the output of the digital data source. The pre-filter has a first output that carries a second sequence of digital signals and a second output that carries a third sequence of digital signals. The second sequence of digital signals is time shifted relative to the third sequence of digital signals. The circuit also includes an interpolation circuit with a first input coupled to the first output of the pre-filter and a second input coupled to the second output of the pre-filter.

Efficient interpolator for high speed timing recovery

The invention provides an apparatus for decoding a coded digital data sequence. The apparatus includes a first Viterbi decoder of a first response type, a first filter and a second filter. The first and second filters are coupled to receive decoded sequences from the first Viterbi decoder. The first Viterbi decoder generates a first decoded sequence from the coded digital data sequence. The first and second filters generate respective first and second error signals in response to receiving the first decoded sequence. The first and second error sequences indicate differences between the first decoded sequence and second and third decoded sequences, respectively. The second and third decoded sequences are probable sequences produced by Viterbi decoders of respective second and third response types in response to receiving the coded digital data sequence.

Processor for digital data

A baud rate digital timing recovery circuit for use in the read channel of a storage device controller is able to operate nominally at the baud rate by recognizing and compensating for oversampling and undersampling conditions. The read channel includes a sample rate converter for interpolating between digitally sampled values and a digital timing recovery loop that detects a phase error in the interpolated signal and adjusts the interpolation interval accordingly. An accumulator circuit generates a modulo-TS interpolation interval value, where TS is the sampling period. Detection circuitry detects when the interpolation interval value has wrapped through its maximum value or minimum value and generates an oversampling or undersampling signal in response. The oversampling and underampling signals are received by an elastic buffer. The elastic buffer operates to store extra values that are generated during undersampling conditions and also disregards bogus samples that are generated during oversampling conditions, in response to the undersampling and oversampling signals. A mini-elastic buffer, also responsive to the oversampling and undersampling signals may be employed in the phase detection loop. The system can operate at the nominal baud rate or can operate at a half baud rate with two parallel paths for processing two incoming samples with each clock cycle.

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County Offaly, Ireland

Thomas J Conway