Compaq Computer Corporation, Inc.

Hewlett-packard Development Company, L.p.

Compaq Information Technologies Group, L.p.

Other

Hewlett Packard Enterprise Development LP

Thomas J Bonola

Michael P Moriarty

Sompong Paul Olarig

John M Hemphill

Mike Dickson

Michael R Garrett

Michael F Angelo

Robert C Brooks

James M Mann

Kent E Biggs

Brian T Purcell

Harold Merkel

Mark W Welker

Richard E Hodges

Lorri L Jefferson

Derek Labron Everett

Yolanda Maria Rivas

John Edward Larson

Thanh Thien Tran

Kevin G Depew

John MacLaren

Craig Walrath

Charles N Shaver

Scott P Faasse

Chi Kim Sides

John Harsany

Ramkrishna V Prakash

Mark L Hammons

Jerry Johnson

Robert D Herrington

Michael P Medina

Examples disclosed herein relate to a conference call host. Examples include to establishing, by a first computing system, a first secure connection to a second computing system via a wireless network in response to receiving a secure connection request from the second computing system; the first computing system and the second computing system are in physical proximity to each other. Examples include to provide an operating system session to the second computing system through the secure connection while the first computing system and the second computing system remain in physical proximity to each other; the operating system is stored on and executable by the first computing system. Examples include to provide a connection to a conferencing platform to the second computing system via the first secure connection, the conference call at least among the first computing system, the second computing system, and a remote user.

Host a conference call

A data processing system supports remote graphics console and virtual media access to virtual machines. The data processing system is configured for usage with a virtualization platform that runs multiple operating systems simultaneously on at least one physical server. The data processing system comprises a virtual keyboard/video/mouse (KVM) element integrated into the virtualization platform and is configured to generate a remote management graphics console and map virtual media into the operating system plurality.

Remote graphics console and virtual media access to virtual machine guests

A method for transferring management data between processors over an Input/Output (I/O) bus system () includes receiving the management data at a managing processor () from a managed host processor () over the I/O bus system; and storing the management data in an addressable memory () of an I/O bus interface device () of the managing processor ().

Management data transfer between processors

Certain embodiments of the present invention are directed to providing efficient and easily-applied mechanisms for inter-core and inter-processor communications and inter-core and inter-processor signaling within multi-core microprocessors and certain multi-processor systems. In one embodiment of the present invention, local advanced programmable interrupt controllers within, or associated with, cores of a multi-core microprocessor and/or processors of a multi-processor system are enhanced so that the local advanced programmable interrupt controllers can be configured to automatically generate inter-core and inter-processor interrupts when WRITE operations are directed to particular regions of shared memory.

Method and system for generating and delivering inter-processor interrupts in a multi-core processor and in certain shared memory multi-processor systems

A data processing system transforms a physical server into multiple virtual servers. The illustrative data processing system comprises a physical server and a virtualization platform integrated into the physical server that is configured to run multiple operating systems simultaneously one or more physical servers. A baseboard management controller integrated into the physical server controls the virtualization platform and the operating systems including physical and virtual resources. The virtualization platform operates according to state data accessed from the baseboard management controller.

Server virtualized using virtualization platform

In one embodiment, a computer system comprises a host machine comprising a plurality of compute resources, at least one management processor, a hypervisor, at least one persistent state data store location coupled to the host machine, wherein the persistent state data store location stores configuration data for the hypervisor, and a persistent state module coupled to a management processor coupled to the host machine, wherein the persistent state module maps hypervisor configuration data to a persistent state data store.

Method and apparatus for configuring a hypervisor during a downtime state

A data processing system enables configuration of a virtual connect functioning in combination with a virtualization platform. The illustrative data processing system is used with a virtualization platform which is configured to run multiple operating systems simultaneously on one or more physical servers and a virtual connect device which is communicatively coupled to the virtualization platform. The virtual connect device virtualizes connections between the physical server or servers and a network infrastructure. The data processing system comprises a configuration manager that integrates migration and failover of virtual machines operating under the virtualization platform with migration and failover of physical servers operative under the virtual connect device for management of virtual and physical migration and failover using common commands.

Virtualization platform configured with virtual connect control

A computing system supports a virtualization platform with dedicated cache access. The computing system is configured for usage with a memory and a cache and comprises an instruction decoder configured to decode a cache-line allocation instruction and control logic. The control logic is coupled to the instruction decoder and controls the computing system to execute a cache-line allocation instruction that loads portions of data and code regions of the memory into dedicated cache-lines of the cache which are exempted from eviction according to a cache controller replacement policy.

Virtualization platform with dedicated cache access

The present disclosure describes exemplary embodiments of BIOS-based systems and methods of processor power management. Such systems include a computer system, comprising: a processor operable at a plurality of power levels (the processor comprises a register capable of storing a processor load value); a memory coupled to the processor; and BIOS software stored in the memory that executes on the processor, (the BIOS software comprises a power management module). The power management module sets the processor to a new power level of the plurality of power levels if a function of the load value indicates the new power level.

BIOS-based systems and methods of processor power management

A memory subsystem may be usable in an electronic system. The memory subsystem may comprise a memory controller and a plurality of memory modules coupled to the memory controller. The memory module may be isolated wherein transactions that target the isolated memory module can complete without loss of data and without accessing the isolated memory module, and while isolated, the memory module can be tested.

Memory testing

A secure boot environment may be provided that includes a secure memory isolated but accessible to a coupled processing device. The secure memory may store and provide boot strap instruction to the processing device. In addition, a authentication system may be provided to ensure secure access to the secure memory.

Method and apparatus for offloaded enhanced boot process

The specification discloses a heap memory management system in which software streams remove and replace blocks of heap memory from the heap pile, managed in a linked list fashion, in a last-in/first-out fashion at the top of the list. A hardware device returns blocks of heap memory, and this return is to the end or bottom of the linked list. In this way, software streams may remove and return blocks of heap memory simultaneously with hardware devices returning blocks of heap memory.

Method for providing concurrent non-blocking heap memory management for fixed sized blocks

In a computer system having at least one host processor, a method and apparatus for providing seamless hooking and interception of selected entrypoints includes finding the IDT for each CPU which can include scanning the HAL image for the HAL PCR list. Saving the interrupt handler currently mapped in the CPU's interrupt descriptor table. Patching the original interrupt into the new interrupt handler. Storing the new interrupt exception into the CPU's interrupt descriptor table. Hooking a select entrypoint by first determining if the entrypoint begins with a one byte instruction code. If it does, saving the address of the original entrypoint, saving the original first one byte instruction, and patching the new interrupt intercept routine to jump to the original entrypoint's next instruction.

Method and apparatus for providing seamless hooking and intercepting of selected kernel and HAL exported entry points

A data transaction controller for transferring data responsive to a request from a client. The data transaction controller includes channel circuitry for providing a channel for data transfers. The channel circuitry includes a first storage device for storing channel configuration data. The data transaction controller further includes control circuitry for controlling access by the client to the channel circuitry.

Growing community of inventors

Magnolia, TX, United States of America

Thomas J Bonola