International Business Machines Corporation

Thomas J Bardsley

James Stephen Mason

Philip J Murfet

Matthew R Cordrey-Gale

Jeremy K Stephens

Huihao Xu

Matthew B Baecher

Charlie Chornglii Hwang

Gareth John Nicholls

Mark R Taylor

Joseph O Marsh

Jed R Eastman

Timothy Michael Kemp

Eugene R Atwood

Robert Michael Bunce

Brian Joel Schuh

Victor Moy

Michael Won

Gareth J Nickolls

Embodiments of the present invention provide an inequality indication system (IIS). The IIS provides built in test support which enables evaluation, in an on-chip digital logic circuit, of digital values as inequalities, with either a single pass/fail bit expressed on a device I/O or a readable register containing inequality evaluation results. The IIS enables the movement of value evaluation onto the device (chip) using a common simple method, well suited to address/data type structures or scan based structures, instead of off-chip, which then requires tester dependent custom code. The IIS, when enabled, overrides the TDO signal to allow it to function as an inequality indicator instead of a standard test data out signal.

Digital test system and method for value based data

A method of varying the gain of an amplifier and an amplifier array are provided. The amplifier array includes two or more amplifier stages () connected in parallel with each amplifier stage having a gain control means. Input signal means () are provided for each amplifier stage with the input signals of the amplifier stages being of different amplitude. Means for enabling and disabling an amplifier stage () are provided and means for summing the outputs of the enabled amplifier stages obtain an output signal (). The gain of the amplifier array has a range from a low gain setting with a first amplifier stage () enabled, through increasing gain settings as the gain of the first amplifier stage is increased from a minimum to a maximum gain, a second amplifier stage () can then be enabled in addition to the first amplifier stage and the gain of the second amplifier stage increased from a minimum to a maximum gain, further amplifier stages are enabled as available up to a maximum gain setting for the amplifier array. Each amplifier stage that is enabled has a decreasingly attenuated input signal and a final amplifier stage to be enabled has a full input signal ().

Variable gain amplifier

Digital testing of an analog driver circuit is enabled using a circuit including a control circuit for generating signals, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit, and a differential receiver circuit for converting the differential output signal to a single ended signal and transmitting the single ended signal. The testing includes skewing a differential output termination impedance, adjusting a differential receiver circuit voltage offset, selecting a differential driver circuit power level, enabling a decoder which activates only one differential driver circuit segment per test sequence, activating a segment, stimulating the differential driver circuit with digital test patterns, receiving differential driver circuit output, converting the output to a single-ended signal, and observing the single-ended signal.

System and method of digitally testing an analog driver circuit

A circuit of testing an analog driver circuit using digital scan-based test methodologies. The circuit of the present invention includes a control circuit for generating signals in response to a test enable signal, a differential driver circuit for receiving a differential input signal, amplifying the differential input signal and transmitting a differential output signal in response to the differential input signal and the signals generated by the control circuit, a programmable termination impedance circuit for generating a differential termination impedance at the output node of the differential driver circuit in response the signals generated by the control circuit, and a differential receiver circuit for receiving the differential output from the differential driver circuit, convert the differential output signal to a single ended signal and transmitting the single ended signal, all in response to the test enable signal.

System of digitally testing an analog driver circuit

An integrated circuit real-time data tracing apparatus for analyzing microprocessor based computer systems for monitoring, in real-time, parameters sufficient to define the load and store operations information that the embedded core controller may assert, and process information during events. Integral on this single chip apparatus is a data trace unit designed to access control, address, and data signal lines required to monitor the embedded core controller's activities; perform data tracing independent of instruction tracing; synchronize with an instruction trace stream; allow for selection of multiple ranges for data tracing; report lost events to a FIFO array; and, output strobe signals to give a cycle accurate indication of when an event has been captured.

Integrated real-time data tracing with low pin count output

A test fixture for use with an improved multi-chip-module wherein the multi-chip-module has a plurality of chips on the top surface, the module having at least one net associated with the chips completely embedded within the substrate and wherein at least one pad is attached to the bottom surface of the substrate and a conductive path provided between the pad and the net. The test fixture includes a zero-insertion-force socket having at least one socket pin having a surface for conductively contacting the pad on the multi-chip-module and extending through the socket and a circuit board having a plurality of inlets for conductively receiving the socket pins including the socket pin contacting the pad.

Multi-chip module with accessible test pads and test fixture

An improved multi-chip-module having a substrate having top and bottom surfaces, a plurality of chips on the top surface, a plurality of pins on the bottom surface, each chip having at least one lead extending through the substrate and conductively coupled to a corresponding pin, the module having at least one net associated with the chips and completely embedded within the substrate, the improvement comprising at least one pad attached to the bottom surface of the substrate, and a conductive path conductively coupled between the pad and the net.

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Poughkeepsie, NY, United States of America

Thomas J Bardsley