Texas Instruments Corporation

Thomas J Aton

James Walter Blatchford

Scott William Jessen

Theodore Warren Houston

Shivaling S Mahant-Shetti

Carl Albert Vickery, Iii

Robert L Pitts

Yong Seok Choi

Shane R Palmer

John Neal Randall

Donald L Plumton

Gregory Charles Baldwin

Steven Lee Prins

Jerold A Seitchik

Denis F Spicer

Robert Soper

Roger Mark Terry

Scott D Jantz

Oh-Kyong Kwon

Satwinder S Malhi

Ajit P Paranjpe

Masashi Hashimoto

Frank Scott Johnson

William R McKee

Benjamen M Rathsack

George R Doddington

Kendall S Wills

Youn Sung Choi

Ashesh Parikh

Kayvan Sadra

Mark G Harward

Derek J Smith

Benjamin P McKee

Basavaraj I Pawate

Lakshmikantha V Holla

Leigh Ann Files

Thirumalai Sridhar

Jimmy W Hosch

Mi-Chang Chang

Oluwamuyiwa Oluwagbemiga Olubuyide

Rebecca J Gale

Phillip Chapados, Jr

Steve Prins

David E Littlefield

Warren L Bean

Rebeca J Gale

Dharaneedharan S

Shivaling S Mahant-Shitti

Rey M Rincon

John S Bartlett

Integrated circuit () includes substrate () with surface () and structure () including base levels (.(+1)), terminating cells (), and block () of standard cells arranged in rows (.(+1)), and another type of block () outside block (). Standard cells at at least two edges of block () have the following protections: (1) block () has strip of separation () having at least a minimum width from the edges of block (), and protected by one of the following: (2) terminating cells () reduce context effect and some terminating cells () are placed at at least one end of rows (.(+1)) of standard cells within first-named block (), and () the terminating cells () reduce context effect and some terminating cells () are at one end of a column of standard cells within block (). Other structures, devices, and processes are also disclosed.

Integrated circuits and processes for protection of standard cell performance from context effects

An integrated circuit containing an array of SRAM cells with T-shaped contacts in the inverters, in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. The drain connecting segments may also extend beyond gate connecting segments by a distance greater than one-third of the width of the gate connecting segments. A process of forming an integrated circuit containing an array of SRAM cells with T-shaped contacts in which drain connecting segments may extend beyond gate connecting segments by a distance greater than 10 percent of a separation distance between ends of opposite drain connecting segments. A process may also form the drain connecting segments to extend beyond gate connecting segments by greater than one-third of the width of the gate connecting segments.

SRAM cell with T-shaped contact

Integrated circuit () includes substrate () with surface () and structure () including base levels (.(+1)), terminating cells (), and block () of standard cells arranged in rows (.(+1)), and another type of block () outside block (). Standard cells at at least two edges of block () have the following protections: (1) block () has strip of separation () having at least a minimum width from the edges of block (), and protected by one of the following: (2) terminating cells () reduce context effect and some terminating cells () are placed at at least one end of rows (.(+1)) of standard cells within first-named block (), and (3) the terminating cells () reduce context effect and some terminating cells () are at one end of a column of standard cells within block (). Other structures, devices, and processes are also disclosed.

An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.

Method of forming a transistor with an active area layout having both wide and narrow area portions and a gate formed over the intersection of the two

A method of aligning a new pattern to more than one previously defined pattern during the manufacture of an integrated circuit. A method of aligning a photolighography pattern reticle to a first previously defined pattern in a first direction and also aligning the photolithography pattern reticle to a second previously defined pattern in a second direction. A method of aligning a photolighography pattern reticle to two previously defined patterns in the same direction.

Alignment to multiple layers

Layout method to minimize context effects and die area

A semiconductor memory cell includes a set of circuit structures, each having column input/output circuits. The semiconductor memory cell further includes a set of replicas corresponding to the column input/output circuits. The set of replicas are non-functional and fills an empty space next to the column input/output circuits and hence, provides context protection for the column input/output circuits.

Context protection for a column interleaved memory

A method of forming an IC including MOS transistors includes using a gate mask to form a first active gate feature having a line width Wover an active area and a neighboring dummy feature having a line width 0.8 Wto 1.3 W. The neighboring dummy feature has a first side adjacent to the first active gate feature, and a nearest gate level feature on a second side opposite the first side. The neighboring dummy feature defines a gate pitch based on a distance to the first active gate feature or the neighboring dummy feature maintains a gate pitch in a gate array including the first active gate feature. The spacing between the neighboring dummy feature and the nearest gate level feature (i) maintains the gate pitch or (ii) provides a SRAF enabling distance that is &#x2267;2 times the gate pitch and the gate mask includes a SRAF over the SRAF distance.

Gate CD control using local design on both sides of neighboring dummy gate level features

An integrated circuit (IC) die has an on-die parametric test module. A semiconductor substrate has die area, and a functional IC formed on an IC portion of the die area including a plurality of circuit elements configured for performing a circuit function. The on-die parametric test module is formed on the semiconductor substrate in a portion of the die area different from the IC portion. The on-die parametric test module includes a reference layout that provides at least one active reference MOS transistor, wherein the active reference MOS transistor has a reference spacing value for each of a plurality of context dependent effect parameters. A plurality of different variant layouts are included on the on-die parametric test module. Each variant layout provides at least one active variant MOS transistor that provides a variation with respect to the reference spacing value for at least one of the context dependent effect parameters.

On-die parametric test modules for in-line monitoring of context dependent effects

A mask build system includes a program for configuring mask layers and a fabrication site for compiling configured mask layers. The system includes at least one database configured by a system processor, the database comprising drawn layers for fabricating reticles of a semiconductor device; and a marker layer configured to define layer dependent features, the marker layer handed off with that part of the at least one database which will support subsequent layers of the database without altering flow of mask build at the fabrication site.

Marker layer to facilitate mask build with interactive layers

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Dallas, TX, United States of America

Thomas J Aton