Advanced Micro Devices Corporation

Globalfoundries Inc.

Asml Netherlands B.v.

Thomas Ingolf Wallow

Ryoung-han Kim

Harry Jay Levinson

Jongwook Kye

Uzodinma Okoroanyanwu

Adam Lyons

Bruno M LaFontaine

Yunfei Deng

Obert Reeves Wood, Ii

Gerard M Schmid

Wim Tjibbo Tel

Robert John Socha

Moshe E Preil

Richard Farrell

Bruno M La Fontaine

Ji Xu

Hermanus Adrianus Dillen

Yuansheng Ma

Adam R Pawloski

Jun Chen

Alden R Acheta

Bart Laenens

Mir Farrokh Shayegan Salek

Yi-Hsing Peng

Peng-cheng Yang

A method for scanning a sample by a charged particle beam tool is provided. The method includes providing the sample having a scanning area including a plurality of unit areas, scanning a unit area of the plurality of unit areas, blanking a next unit area of the plurality of unit areas adjacent to the scanned unit area, and performing the scanning and the blanking the plurality of unit areas until all of the unit areas are scanned.

Method for scanning a sample by a charged particle beam system

A method including providing a plurality of unit cells for a plurality of gauge patterns appearing in one or more images of one or more patterning process substrates, each unit cell representing an instance of a gauge pattern of the plurality of gauge patterns, averaging together image information of each unit cell to arrive at a synthesized representation of the gauge pattern, and determining a geometric dimension of the gauge pattern based on the synthesized representation.

Method and apparatus for pattern correction and verification

A method including obtaining a plurality of gauges of a plurality of gauge patterns for a patterning process, each gauge pattern configured for measurement of a parameter of the patterning process when created as part of the patterning process, and creating a selection of one or more gauges from the plurality of gauges, wherein a gauge is included in the selection provided the gauge and all the other gauges, if any, of the same gauge pattern, or all of the one or more gauges of the same gauge pattern linked to the gauge, pass a gauge printability check.

Gauge pattern selection

Provided is a process including: obtaining a layout specifying, at least in part, a pattern to be transferred to a substrate via a patterning process and an etch process; and modifying, with one or more processors, the layout to include an etch-assist feature that is larger than a resolution limit of the patterning process and smaller than a resolution limit of the etch process, the etch-assist feature being configured to reduce a bias of the patterning process or the etch process, to reduce an etch induced shift of a feature in the layout due to the etch process, or to expand a process window of another patterning process.

Etch-assist features

A process of calibrating a model, the process including: obtaining training data including: scattered radiation information from a plurality of structures, individual portions of the scattered radiation information being associated with respective process conditions being characteristics of a patterning process of the individual structures; and calibrating a model with the training data by determining a ratio relating a change in one of the process characteristics to a corresponding change in scattered radiation information.

Optical metrology of lithographic processes using asymmetric sub-resolution features to enhance measurement

Approaches for utilizing laser annealing to optimize lithographic processes such as directed self assembly (DSA) are provided. Under a typical approach, a substrate (e.g., a wafer) will be subjected to a lithographic process (e.g., having a set of stages/phases, aspects, etc.) such as DSA. Before or during such process, a set of laser annealing passes/scans will be made over the substrate to optimize one or more of the stages. In addition, the substrate could be subjected to additional processes such as hotplate annealing, etc. Still yet, in making a series of laser annealing passes, the techniques utilized and/or beam characteristics of each pass could be varied to further optimize the results.

Optimizing lithographic processes using laser annealing techniques

According to one exemplary embodiment, a method for forming a photoresist pattern on a semiconductor wafer includes forming a photoresist including an organic polymer matrix on the semiconductor wafer. The method further includes exposing the photoresist to a patterned radiation. The method further includes baking the photoresist after exposing the photoresist to the pattern radiation. The method further includes applying an oxidizing reagent to the photoresist to create the photoresist pattern corresponding to the patterned radiation.

Method for forming a photoresist pattern on a semiconductor wafer using oxidation-based catalysis

A method for forming a semiconductor device is provided including processing a wafer having a target material, forming a multilevel photoresist structure having a protection layer over the target material, and forming a multilevel recess in the target material with the multilevel photoresist structure.

Method of forming semiconductor device with multiple level patterning

In one disclosed embodiment, a method for producing a high resolution resist pattern on a semiconductor wafer comprises depositing a blanket layer of material on a semiconductor wafer, forming a resist interaction substrate on the blanket layer of material, forming a resist layer of a pre-determined thickness on the resist interaction substrate, exposing the resist layer to a patterned radiation, and developing the resulting high resolution resist pattern. In one embodiment, patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, patterned radiation may be provided by an electron beam, or ion beam, for example. In one embodiment, the resist layer comprises a chemically amplified resist utilizing a photogenerated acid (PGA), and having a sublayer. In other embodiments, the resist layer includes an additive, for example, fullerite. One disclosed embodiment involves use of an ultra-thin resist layer in combination with a gold resist interaction substrate.

Method for producing a high resolution resist pattern on a semiconductor wafer

Ultrafine dimensions are accurately and efficiently formed in a target layer using a spacer lithographic technique comprising forming a first mask pattern, forming a cross-linkable layer over the first mask pattern, forming a cross-linked spacer between the first mask pattern and cross-linkable layer, removing the cross-linkable layer, cross-linked spacer from the upper surface of the first mask pattern and the first mask pattern to form a second mask pattern comprising remaining portions of the cross-linked spacer, and etching using the second mask pattern to form an ultrafine pattern in the underlying target layer. Embodiments include forming the first mask pattern from a photoresist material capable of generating an acid, depositing a cross-linkable material comprising a material capable of undergoing a cross-linking reaction in the presence of an acid, and removing portions of the non-cross-linked layer and cross-linked spacer from the upper surface of the first mask pattern before removing the remaining portions of the first mask pattern and remaining noncross-linked layer.

Spacer lithography

In one disclosed embodiment, a method for forming a high resolution resist pattern on a semiconductor wafer involves forming a layer of resist comprising, for example a polymer matrix and a catalytic species, over a material layer formed over a semiconductor wafer; exposing the layer of resist to patterned radiation; and applying a magnetic field to the semiconductor wafer during a post exposure bake process. In one embodiment, the patterned radiation is provided by an extreme ultraviolet (EUV) light source. In other embodiments, the source of patterned radiation can be an electron beam, or ion beam, for example. In one embodiment, the polymer matrix is an organic polymer matrix such as, for example, styrene, acrylate, or methacrylate. In one embodiment, the catalytic species can be, for example, an acid, a base, or an oxidizing agent.

Method for forming a high resolution resist pattern on a semiconductor wafer

A method for forming a semiconductor device is provided including processing a wafer having a target material; forming a first pattern over the target material; forming a protection layer over the first pattern; and forming a second pattern, over the target material and not over the protection layer, without an etching step between the forming the first pattern and the forming the second pattern.

Method of forming semiconductor device

Photolithography methods using BARCs having graded optical properties are provided. In an exemplary embodiment, a photolithography method comprises the steps of depositing a BARC overlying a material to be patterned, the BARC having a refractive index and an absorbance. The BARC is modified such that, after the step of modifying, values of the refractive index and the absorbance are graded from first values at a first surface of the BARC to second values at a second surface of the BARC. The step of modifying is performed after the step of depositing.

Methods for performing photolithography using BARCs having graded optical properties

According to one exemplary embodiment, a method for determining a power spectral density of an edge of at least one patterned feature situated over a semiconductor wafer includes measuring the edge of the at least one patterned feature at a number of points on the edge. The method further includes determining an autoregressive estimation of the edge of the at least one patterned feature using measured data corresponding to a number of points on the edge. The method further includes determining a power spectral density of the edge using autoregressive coefficients from the autoregressive estimation. The method further includes utilizing the power spectral density to characterize line edge roughness of the at least one patterned feature in a frequency domain.

Growing community of inventors

San Carlos, CA, United States of America

Thomas Ingolf Wallow