Infineon Technologies Ag

Infineon Technologies Austria Ag

Infineon Technologies LLC

Intel Mobile Communications Gmbh

Thomas Herndl

Gerald Holweg

Walther Pachler

Dirk Hammerschmidt

Bernhard Goller

Burkhard Becker

Norbert Druml

Markus Dielacher

Martin Flatscher

Hannes Plank

Guenter Hofer

Jens Berkmann

Christoph Steffan

Manfred Greschitz

Wolfgang Haas

Theresa Egger

Horst Theuss

Christian Drewes

Werner Weber

Franz Michael Darrer

Albert Auburger

Manfred Zimmermann

Jakob Jongsma

Rainer Matischek

Wolfgang Dettmann

Jürgen Niederholz

Joachim Weitzel

Herbert Roedig

Christian Hambeck

Armin Häutle

Robert Kappel

Gerald Hodits

Sasha Simeunovic

Nicolas Falleau

Florian Grimminger

Stefan Mahlknecht

Michael Holstätter

Michael HOFSTÄTTER

A localization apparatus includes: a time-of-flight circuit configured to emit a first modulated light signal and to receive reflections of the first modulated light signal from at least three devices; a processing circuit configured to determine, based on the first modulated light signal and the reflections, positions of the at least three devices in a first coordinate system associated with the apparatus; and a receive circuit configured to receive second modulated signals from the at least three devices, the second modulated signals including data indicating positions of the at least three devices in a second coordinate system. The processing circuit is further configured to determine a position and orientation of the apparatus in the second coordinate system based on the positions of the at least three devices in the first coordinate system and the data indicating the positions of the at least three devices in the second coordinate system.

Localization apparatus and method

An apparatus for localizing a first device includes a time of flight circuit configured to emit a first modulated light signal and receive a reflection of the first modulated light signal from the first device. The apparatus further includes a processing circuit configured to determine, based on the first modulated light signal and the reflection, a position of the first device in a first coordinate system associated with the apparatus. The processing circuit is further configured to determine, based on the position of the first device in the first coordinate system, a position of the apparatus in a second coordinate system and an orientation of the apparatus in the second coordinate system. The apparatus further includes a transmit circuit configured to emit a second modulated signal to the first device, wherein the second modulated signal includes data indicating the position of the first device in the second coordinate system.

Apparatus and method for localizing a first device, localization apparatus and methods for localization

A functional skin patch having a first surface and a second surface opposite the first surface is provided. The functional skin patch includes a functional unit having a thermo harvester and an antenna unit. The thermo harvester has a first terminal thermally connected to the first surface and a second terminal. The antenna unit has a first terminal thermally connected to the second terminal of the thermo harvester and a second terminal thermally connected to the second surface. The antenna unit has a stacked layer structure including, in this sequence, a metal layer thermally connected to the second terminal of the thermo harvester, a ferrite layer thermally connected to the metal layer, and an antenna layer thermally connected to the ferrite layer.

Functional skin patch

A semiconductor device includes a semiconductor substrate having an upper first main face and first and second recess areas formed in the upper first main face, a battery arranged at the first recess area and one or more of a shock sensor and an acceleration sensor arranged at the second recess area. The shock sensor or the acceleration sensor includes a movable mass, a cantilever connected to the moveable mass, a piezoelectric layer applied to the cantilever, and a wiring connected to the piezoelectric layer. The wiring has first and second terminals. The moveable mass and part of the cantilever are arranged above the second recess area, so that the shock sensor or the acceleration sensor delivers a voltage between the first and second terminals, a strength of the voltage being dependent on a strength of a shock or acceleration exerted on the semiconductor device.

Semiconductor device having one or more of a shock sensor and an acceleration sensor

A communication arrangement may include a communication device, which may include an application processor, a mobile radio circuit, and a near-field communication (NFC) circuit configured according to an NFC technology for transmission of data and energy for operating a circuit external to the communication device. The arrangement may include a flexible carrier mounted detachably on the communication device. The carrier may include a radio circuit, an NFC circuit configured according to an NFC technology, a circuit coupled to the NFC circuit and the radio circuit, which is configured to be operated with energy which is received by means of the NFC circuit according to the NFC technology, the circuit configured for converting data coded in accordance with the NFC technology into data coded in accordance with the radio technology, or for converting data coded in accordance with the radio technology into data coded in accordance with the NFC technology.

Communication arrangement

A semiconductor device includes a semiconductor substrate, a battery attached to the semiconductor substrate, and a sensor attached to the semiconductor substrate. The battery is electrically connected to the sensor and configured to supply the sensor with electrical power.

Semiconductor device and an identification tag

Various embodiments provide a chip. The chip has a carrier, an integrated circuit formed above the carrier, and an energy storage element. The energy storage element has a first electrode and a second electrode and is used to supply the integrated circuit with electrical energy. The carrier, the integrated circuit and the energy storage element are monolithically formed, the first electrode being formed from the carrier.

Chip, chip arrangement and method for producing a chip

An integrated circuit chip includes an output node, receiver front ends, and control logic. The receiver front ends are configured to receive an input signal. Each of the receiver front ends is configured to receive the input signal and provide an output signal at the output node. At least one of the receiver front ends is configured to selectively consume less power. The control logic is configured to select the number of receiver front ends providing an output signal to the output node based on a received signal strength indication.

System including receiver front ends

In various embodiments, a chip arrangement includes a first chip having a first antenna which is monolithically integrated in the first chip and is intended to communicate with at least one of an external reader or an external writer; a second chip having a second antenna which is monolithically integrated in the second chip and is intended to communicate with the at least one of the external reader or the external writer; and a booster antenna which is coupled to the first antenna in a first coupling area in order to increase a range of the first antenna and is coupled to the second antenna in a second coupling area in order to increase a range of the second antenna.

Chip arrangement, analysis apparatus, receiving container, and receiving container system

One embodiment of the present invention relates to an analog correlation unit comprising a plurality of parallel correlation components configured to operating according to an advanced switched-capacitor low pass filter principle that increases coding gain of the unit. Each correlation component comprises a sampling stage and a correlation stage. The sampling stage may comprise a switched capacitor configured to sample a received baseband signal to determine a value (e.g., polarity) of the baseband signal. The sampled baseband signal is provided to the correlation stages, which may respectively comprise a plurality of switched integrators configured to selectively receive and integrate the sampled baseband signal over time depending upon values (e.g., polarity) of the correlation code to generate voltage potential values. The analog correlation result is evaluated by a comparison of an adjustable threshold voltage with the difference between the output voltage potential values.

Analog correlation technique for ultra low power receivers

A system including an output node and receiver front ends. The receiver front ends are configured to receive an input signal. Each of the receiver front ends is configured to receive the input signal and provide an output signal at the output node. At least one of the receiver front ends is configured to selectively consume less power.

A device for detecting a measured quantity has a sensor chip for detecting the measured quantity, a supply for providing a power supply, and an injection-molded enclosure for accommodating the sensor chip and the supply, the injection-molded enclosure including integrated conductive traces providing an electrical connection between the sensor chip and the supply.

Sensor component and method for producing a sensor component

A device and associated method for passing parameters to a finger in a rake receiver are disclosed. The finger is initially operated with a first parameter set which is held in a first memory area (PAR_RAM). To change the parameter set, a second parameter set is loaded into a second memory area (PAR_CHG_RAM), a check is carried out to determine whether a switching condition (SCHED_RAM) is satisfied, and if it is an access for that finger is switched (MUX) from the first memory area (PAR_RAM) to the second memory area.

Method and device for passing parameters to rake receiver

Depending on the sequence of the decoded payload signal bits (a, . . . , a) and redundancy checking bits (p, . . . , p) which are produced by the Viterbi traceback, either some of these bits are inserted by means of a distribution device () from the front into a linear feedback shift register (), or some of these bits are inserted by means of the distribution device () from the rear into a linear feedback shift register (), or all of them are inserted into a linear feedback shift register () from the rear with the allocated coefficients being unchanged, or all of them are inserted into a shift register from the front with the allocated coefficients being inverted. This allows a redundancy checking process to be carried out on a transmitted data block in the shift register () without temporary storage of the bits produced by the decoding process.

Parallel processing for decoding and cyclic redundancy checking for the reception of mobile radio signals

A decoding apparatus includes at least one decoder both for a turbo-decoding and for a Viterbi decoding, at least one first data path for the Viterbi decoding of a convolution code, at least one second data path for the decoding of a turbo code, and a common memory having a multiplicity of individual memory areas. It is possible to allocate at least one memory area both through the first data path in the Viterbi mode and through the second data path in the turbo mode. The invention also includes a trellis processor and a method for operating a decoding apparatus in which at least parts of the first data path and of the second data path can be utilized jointly both for the turbo decoding and for the Viterbi decoding.

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Biedermannsdorf, Austria

Thomas Herndl