International Rectifier Corporation

Infineon Technologies Americas Corp.

Infineon Tecimologies Americas Corp.

Thomas Herman

Alexander Lidow

Robert A Beach

Jianjun Cao

Kyle A Spring

Vladimir Rumennik

Harold E Davis

Oliver Williams

A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only.

III-nitride power semiconductor device

A power semiconductor device includes a III-nitride heterojunction body including a first III-nitride body and a second III-nitride body having a different band gap than that of the first III-nitride body, a first power electrode coupled to the second III-nitride body, a second power electrode coupled to the second III-nitride body, a gate array arrangement disposed between the first and second power electrodes, and a conductive channel that includes a two-dimensional electron gas that in a conductive state includes a reduced charge region under the gate arrangement that is less conductive than its adjacent regions. The reduced charge region extends beyond an edge of the gate arrangement toward one of the power electrodes only.

A III-nitride power semiconductor device that includes a two dimensional electron gas having a reduced charge region under the gate thereof.

A method for fabrication of a III-nitride film over a silicon wafer that includes forming control joints to allow for overall stress relief in the III-nitride film during the growth thereof.

III-nitride wafer fabrication

A merged gate transistor in accordance with an embodiment of the present invention includes a semiconductor element, a supply electrode electrically connected to a top surface of the semiconductor element, drain electrode electrically connected to the top surface of the semiconductor element and spaced laterally away from the supply electrode, a first gate positioned between the supply electrode and the drain electrode and capacitively coupled to the semiconductor element to form a first portion of the transistor and a second gate positioned adjacent to the first gate, and between the supply electrode and the drain electrode to form a second portion of the transistor, wherein the second gate is also capacitively coupled to the semiconductor element. The first gate is connected to an input voltage signal such that conduction of the first portion is based on a value of the input voltage signal and the second gate is connected to a predetermined constant voltage such that the second portion of the transistor conducts until a voltage difference between the predetermined constant voltage and a voltage at the source electrode reaches a predetermined level.

Merged cascode transistor

A low contact resistance ohmic contact for a III-Nitride or compound semiconductor wafer or die consists of 4 layers of Ti, AlSi, Ti and TiW. The AlSi has about 1% Si. The layers are sequentially deposited as by sputtering, are patterned and plasma etched and then annealed in a rapid thermal anneal process. The use of AlSi in place of pure Al reduces contact resistance by about 15% to 30%.

Aluminum alloys for low resistance, ohmic contacts to III-nitride or compound semiconductor

A starting wafer for high voltage semiconductor devices is formed by implanting arsenic into the top surface of a p type silicon substrate wafer to a depth of about 0.1 micron. A N type non-graded epitaxial layer is then grown atop the substrate without any diffusion step so that the arsenic is not intentionally driven. Device junction are then diffused into the epitaxially grown layer.

Process for resurf diffusion for high voltage MOSFET

A III-nitride power semiconductor device that includes a two dimensional electron gas having a low field region under the gate thereof.

A vertical MOSFET has a substrate of a first conductivity type. A channel region of a second conductivity type is diffused into the substrate. A gate is disposed at least partially over the channel region. A source region of a second conductivity type is disposed proximate to the gate and adjacent to the channel region. The channel region includes a depletion implant area proximate to the gate. The depletion implant species is of the second conductivity type to reduce the concentration of the first conductivity type in the channel region without increasing the conductivity in the drain/drift region.

Depletion implant for power MOSFET

A power MOSFET die with a minimized figure of merit has of a planar stripe MOSFET geometry in which parallel diffused bases (or channels) are formed by implantation and diffusion of impurities through parallel elongated and spaced polysilicon stripes wherein the polysilicon line width is from about 3.2 to 3.4 microns, preferably 3.4 microns; the polyline spacing is from about 1 to 4 microns, preferably 1.5 microns and the diffused bases are spaced by greater than about 0.8 microns. The polysilicon stripes act as masks to the sequential formation of first base stripes, the source stripes and second higher concentration base stripes which are deeper than the first base stripes. Insulation side wall spacers are used to define a contact etch for the source contact. The above design geometry is used for both the forward control MOSFET and the synchronous rectifier MOSFET of a buck converter circuit.

Process for manufacturing a low voltage MOSFET power device having a minimum figure of merit

A vertical conduction MOSFET having a reduced on resistance R as well as reduced threshold voltage V , and an improved resistance to punchthrough and walkout has an extremely shallow source diffusion, of less than 0.3 microns in depth and an extremely shallow channel diffusion, of less than about 3 microns in depth. In a P channel version, phosphorus is implanted into the bottom of a contact trench and into the channel region with an implant energy of 400 keV for a singly charged phosphorus ion or 200 keV for a doubly charged ion, thereby to prevent walkout of the threshold voltage.

MOSFET with reduced threshold voltage and on resistance and process for its manufacture

Low voltage MOSFET power device having a minimum figure of merit

A high power MOSFET is disclosed in which two laterally spaced sources each supply current through respective channels in one surface of a semiconductor chip which are controlled by the same gate. The channels lead from the source electrodes to a relatively low resistivity epitaxially formed region which is deposited on a high conductivity substrate. The epitaxially deposited semiconductor material immediately adjacent and beneath the gate and in the path from the sources to the drain has a relatively high conductivity, thereby to substantially reduce the on-resistance of the device without effecting the breakdown voltage of the device. The breakdown voltage of the device is substantially increased by forming a relatively deep p-type diffusion with a large radius in the n-type epitaxial layer beneath each of the sources.

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Manhattan Beach, CA, United States of America

Thomas Herman