Agere Systems Inc.

Lsi Corporation

Thomas Herbert Shilling

John William Osenbach

Hugo Fernando Safar

Weidong Xie

Ralph Salvatore Moyer

Vivian Wanda Ryan

Patrick Joseph Carberry

Jeffery John Gilbert

George John Libricz, Jr

Juan Alejandro Herbsommer

Bradley Paul Barber

John McKenna Brennan

Timothy Brooks Bambridge

Osvaldo J Lopez

Brian Thomas Vaccaro

Joel Lott

Ahmed Nur Amin

David Lee Crouthamel

LaRue Norman Dunkleberger

Jason Paul Goodelle

Joseph Micheal Freund

Techniques for integrated circuit device fabrication are provided. In one aspect, an integrated circuit device comprises a base, at least one die attached to the base, and a counterbalancing layer on at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die. In another aspect, warping of an integrated circuit device comprising at least one die attached to a base is controlled by applying a counterbalancing layer to at least a portion of at least one side of the base adapted to compensate for at least a portion of a thermal expansion difference existing between the base and the die.

Controlling warping in integrated circuit devices

An assembly comprises a stiffener, a circuit substrate and an IC chip. The stiffener has a surface with a first region and a second region. The circuit substrate covers at least a portion of the first region of the stiffener, while the IC chip overlies at least a portion of each of the first and second regions of the stiffener. The assembly further comprises a signal solder bump and a thermally conductive feature. The signal solder bump contacts the IC chip and the circuit substrate. The thermally conductive feature is disposed between, and is metallurgically bonded to, the integrated circuit chip and the second region of the stiffener. The thermally conductive feature provides an efficient thermal conductivity pathway between the IC chip and the stiffener.

Integrated circuit chip assembly having array of thermally conductive features arranged in aperture of circuit substrate

A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewall interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Semiconductor device package with base features to reduce leakage

An electronic module has a non-conducting substrate having at least one opening and a die/carrier assembly mounted within the opening in the substrate. The assembly has a conducting carrier and one or more integrated circuit (IC) dies mounted to the carrier. The invention may be implemented as an electronic system comprising a circuit board (CB) and at least one such electronic module mounted to the CB.

Packaging for electronic modules

Device packages often include walls build on a heat sink that surrounds a device die that thermally interacts with the heat sink. Use of raised or depressed feature on said heat sink that contacts the walls improves the cohesiveness of the package. By appropriately positioning these features contaminant infusion into the package is improved without degrading cohesiveness.

Device package

A semiconductor device package comprises a container including a base and sidewalls. The base is configured to support a semiconductor device chip, and a lead frame extends through at least one of the sidewalls. A portion of the lead frame within the sidewall has at least one aperture penetrating into the lead frame. The sidewall material extends into the aperture, thereby forming a strong interfacial bond that provides a low leakage, sidewall-lead-frame interface. The base has a reentrant feature that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby forming a low leakage base-sidewalls interface. The top surface of the base has a groove that is positioned within the thickness of at least one of the sidewalls and engages the at least one sidewall, thereby enhancing the low leakage base-sidewall interface.

Semiconductor device package with reduced leakage

In the method, a cap wafer surface is lithographically etched at time of fabrication, so that a raised ridge onto which bonding material is placed is formed near a perimeter of a desired cavity region. This is done in order to reduce the bonding area between the cap wafer and electronic device wafers, so as to provide a better defined standoff. In another aspect of the method, the cap wager surface is lithographically etched to form recesses or trenches near the perimeter of a cavity region, each recess being filled with a sealing material, and polished if necessary to be flush with the cap wafer surface. Thereafter, the cap wafer surface is etched so that the filled recesses become the raised ridges which are used to bond a cap wafer to an electronic device wafer.

Process for packaging electronic devices using thin bonding regions

An apparatus and process to assess the occurrence or the likelihood of a failure in an integrated circuit. The process includes forming a conductive region such as a runner about the periphery of a substrate or die. The conductive regions may be located at one of more different metallization layers within the integrated circuit. The conductive region is couple to one or more of the bond pads. The die is assessed by measuring the resistance, conductivity, cross talk or other electrical characteristics on the conductive region via the bond pads. The assessment can then be used to predict whether, for example, the runners formed in the integrated circuit have failed or are likely to fail.

Integrated circuit and a method of manufacturing an integrated circuit

A process to assess the occurrence or the likelihood of a failure in an integrated circuit. The process includes forming a conductive region such as a runner about the periphery of a substrate or die. The conductive regions may be located at one or more different metallization layers within the integrated circuit. The conductive region is coupled to one or more of the bond pads. The die is assessed by measuring the resistance, conductivity, cross talk or other electrical characteristics on the conductive region via the bond pads. The assessment can then be used to predict whether, for example, the runners formed in the integrated circuit have failed or are likely to fail.

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Macungie, PA, United States of America

Thomas Herbert Shilling