Altera Corporation

Other

Tier Logic, Inc.

Thomas Henry White

Sergey Yuryevich Shumarayev

Rakesh H Patel

Wilson Wong

William Bradley Vest

Dirk Alan Reese

Giles V Powell

Myron Wai Wong

Chiakang Sung

Andy Louie Lee

Joseph Huang

Bonnie I Wang

Khai Nguyen

Yan Chong

Xiaobao Wang

Philip Pan

In Whan Kim

Tzung-Chin Chang

Gopi Rangan

Bradley Jensen

Wuu-Cherng Lin

Dustin Do

Surgey Y Shumarayev

Swee Aun Lau

Raminda U Madurawe

John E Turner

Leo Min Maung

Peter Ramyalal Suaris

Kevin A Norman

Rafael Czernek Camarota

Raminda Udaya Madurawe

Embodiments of N-well or P-well strap structures are disclosed with lower space requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

N-well/P-well strap structures

Embodiments of N-well or P-well strap structures are disclosed with lower requirements achieved by forming the strap on both sides of one or more floating polysilicon gate fingers.

Circuits, methods, and apparatus that provide for protection of configuration bitstreams from theft. One exemplary embodiment receives a scrambled configuration bitstream with an integrated circuit. The scrambled configuration bitstream is descrambled using a plurality of multiplexers under control of a security key. A configuration bitstream is received in portions. One specific embodiment uses a key stored in memory to control a bank of multiplexers that descramble each of the received portions of the configuration bitstream. Other embodiments store longer keys, and use portions of the keys to descramble one or more portions of their respective configuration bitstreams. The outputs of the multiplexers are then stored in configuration memory cells.

FPGA configuration data scrambling using input multiplexers

An integrated circuit fabricated by a mask set including a mask to generate a metal pattern defined by CAD software, the metal pattern generation method including: reading a binary data set, the data points in the set uniquely matched to a plurality of fixed metal tabs; and selecting a metal tab from a first set of selectable metal tabs for a first data value, or a second set of selectable metal tabs for a second data value for each of the fixed metal tabs; wherein a first set metal tab and a second set metal tab couples each said fixed metal tab to first and second voltages respectively.

Automated metal pattern generation for integrated circuits

An integrated circuit with distributed power using through-silicon-vias (TSVs) is presented. The integrated circuit has conducting pads for providing power and ground located within the peripheral region of the top surface. A number of through-silicon-vias are distributed within the peripheral region and a set of TSVs are formed within the non-peripheral region of the integrated circuit. Conducting lines on the bottom surface are coupled between each peripheral through-silicon-via and a corresponding non-peripheral through-silicon-via. Power is distributed from the conducting pads to the TSVs within the non-peripheral region through the TSVs within the peripheral region, thus supplying power and ground to circuits located within the non-peripheral region of the integrated circuit chip.

Distributing power with through-silicon-vias

A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.

MPGA products based on a prototype FPGA

Integrated circuits with memory cells are provided. A memory cell may have four inverter-like circuits connected in a ring configuration and four corresponding storage nodes. The four inverter-like circuits may form a storage portion of the memory cell. Some of the inverter-like circuits may have tri-state transistors in pull-up and pull-down paths. The tri-state transistors may be controlled by address signals. Address and access transistors may be coupled between some of the storages nodes and a data line. The address and access transistors may be used to read and write into the memory cell. During write operations, the address signals may be asserted to turn off the tri-state transistors and eliminate contention current from the cell. During read and normal operations, the address signals may be deasserted to allow the inverter-like circuits to hold the current state of the cell while providing soft error upset immunity.

Memory elements with soft error upset immunity

A power-on-reset circuit determines when it is safe for a programmable device to access configuration data from an associated non-volatile memory following a reset operation. The power-on-reset circuit receives a bandgap reference voltage produced by the programmable device. A comparator circuit is used to trigger a self-clocking delay unit when the bandgap reference voltage reaches a threshold level. The self-clocking delay unit generates its own clock signal independent of the clock frequency of the programmable device. The self-clocking delay unit may use edge-dependent delay units in a feedback loop to generate the clock signal. Using its own clock signal, the self-clocking delay unit waits for a predetermined time period and the outputs a signal to be used to enable access to the associated non-volatile memory.

Process and temperature invariant power on reset circuit using a bandgap reference and a long delay chain

A portable sports equipment rack is provided with two relatively foldable sections. Each section has a top wall and a bottom wall below the top wall. End walls and a rear wall hold the top and bottom walls vertically spaced. Along the front edge of at least one of the bottom walls are located a number of handle receiving structures. At least one hinge joins adjacent end edges of the bottom walls. When the portable sports equipment rack is suspended, chiefly by its ends, the weight of the rack will tend to keep it in an open deployed configuration. The sections can be folded against one another, and held together by a latch. A handle on one of the top walls facilitates carrying of the rack when it is folded. A further embodiment of the sports equipment rack is formed from an assembly of modules, each containing a top wall, bottom wall, sidewalls, rear wall, and handle receiving structures.

Portable sports equipment rack

Techniques and circuitry provide fast, accurate, proper, and reliable transfer of configuration data from an on-chip nonvolatile memory to the programmable logic core of a programmable logic integrated circuit. A first technique includes not allowing the programmable logic to be configured until the data held in the on-chip nonvolatile memory can be read correctly and reliably. A second technique includes verifying the configuration data is transferred from the nonvolatile memory to the programmable logic core correctly and without error during the transfer process. These two techniques may be combined or used individually during the configuration of an integrated circuit.

Techniques for configuring programmable logic using on-chip nonvolatile memory

A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.

Programmable logic device with on-chip nonvolatile user memory

Growing community of inventors

Santa Clara, CA, United States of America

Thomas Henry White