Nxp Usa, Inc.

Freescale Semiconductor,inc.

Stmicroelectronics S.r.l.

Thomas Henry Luedeke

Loic Hureau

Michael Rohleder

Carl Culshaw

Jean-Philippe Meunier

Kumar Abhishek

Vladimir Litovtchenko

Maxime Clairet

Alaa Eldin Y El Sherif

Thomas Koch

Hector Adrian Sanchez

Joseph Charles Circello

Stefano Pietri

Srikanth Jagannathan

Ray Charles Marshall

Sunny Gupta

Markus Baumeister

Garima Sharda

Nicolas Bernard Grossier

Anurag Jindal

Stefan Doll

Nikila Krishnamoorthy

Joachim Kruecken

Markus Regner

Dirk Moeller

Joseph Rollin Wright

Andrew Edward Birnie

Deboleena Sakalley

Stephan G Mueller

Daniel McKenna

Steven K Watkins

Gary Hay

Mohit Satsangi

Alistair Paul Roberston

Hubert Glenn Carson, Jr

Joel Ray Knight

Venkannababu Ambati

Harald Michael Lüpken

Mark Shelton Cinque

James M Giandelone

Christian Steffen

Stephen Robert Traynor

Hilario Manuel Garza

Kamel Musa Khalaf

Adrian Lee Carleton

A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.

Power-on-reset request functionality in semiconductor devices and power management ICs

Monitoring for an over-voltage condition based on a regulated voltage is disclosed. A first terminal of a voltage regulator receives a first voltage which is based on a regulated voltage input to a controller. A second terminal of the voltage regulator receives a second voltage indicative of the voltage input to the controller. A determination is made whether the first voltage exceeds the first voltage reference for a first time window and the controller is reset based on the determination that the first voltage exceeds the first voltage reference. A determination is also made whether the second voltage exceeds the second voltage reference for the second time window and the voltage regulator is powered down on based on the determination that the second voltage exceeds the second voltage reference.

Voltage regulator which redundantly monitors for an over-voltage condition based on a regulated voltage provided to a controller and methods

Power management circuitry includes a power management circuitry having a handshake watchdog (HWD) timer and configured to, upon a reset, set the HWD timer to a maximum delay time allowed between an initial wakeup request received at a first input and a qualified wakeup request expected at a second input and configured to start the HWD timer counting in response to the initial wakeup request. Processing circuitry includes a wakeup signal aggregator configured to receive wakeup signals from internal and external wakeup events and to provide a notification of an occurrence of a wakeup event. The notification is provided as the initial wakeup request. A low power mode sequencer configured to initiate a low power mode exit sequence in response to the notification from the wakeup signal aggregator and to provide the qualified wakeup request as a result of performing at least a portion of the exit sequence.

Processing wakeup requests in a processing system having power management circuitry and a processing circuitry

A GPIO includes a transmitter having an output stage connected to the I/O pad and adapted to supply transmit data to an I/O pad in response to output data generated by a low voltage core logic operating within a functional voltage range for transmit operations; a receiver adapted to supply receive data to the low voltage core logic operating within the functional voltage range in response to input data received at the I/O pad for receive operations; a VLV transmitter adapted to supply VLV transmit data to the output stage of the transmitter and not directly to the I/O pad in response to output test data generated by the low voltage core logic; and a VLV receiver adapted to supply VLV receive data to the low voltage core logic operating within a low core supply voltage range in response to input data received from the output stage of the transmitter.

Very low voltage I/O circuit and method for screening defects

A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.

System and method of power mode management for a processor

A fully digital integrated circuit apparatus () and method () are provided for generating a test mode enable signal with a digital non-resettable state retention storage circuit () connected to store an authentication control pattern for authorizing test mode access to a secure circuit, a digital safety interlock gate circuit () connected to store a safety interlock gate setting that may be accessed independently from a test mode enable signal, and combinatorial logic circuitry () for generating the test mode enable signal only when the interlock safety gate setting is set to a first value and the digital non-resettable state retention storage circuit stores the authentication control code.

Method and apparatus for digital only secure test mode entry

An integrated circuit includes a plurality of external terminal circuits, each having an external terminal. The integrated circuit includes a wakeup detector including a plurality of inputs. Each input of the plurality of inputs is coupled to an external terminal circuit. The wakeup detector generates an output signal indicative of an external terminal of the plurality of external terminal circuits being placed at a wakeup voltage. The integrated circuit includes a trigger generation circuit having a plurality of outputs in which each output is coupled to an external terminal circuit to generate a wake-up voltage at an external terminal of the external terminal circuit by coupling the external terminal to a power supply terminal of the integrated circuit to generate an indication of the external terminal being at the wakeup voltage at the wakeup detector when at least a portion of the integrated circuit is in a low power mode.

Low power mode testing in an integrated circuit

The present invention provides a monitor, especially a wake up monitor, for monitoring an integrated circuit, the monitor comprising a first monitoring unit configured to monitor at least one input of the integrated circuit, a second monitoring unit configured to monitor at least one output of the integrated circuit, a measurement unit configured to measure the time elapsed between an event on the at least one input and a reaction to the event on the at least one output and configured to output an alert signal if the elapsed time exceeds a predetermined first time limit. The present invention furthermore discloses an integrated circuit and a method for monitoring an integrated circuit.

Monitor, integrated circuit and method for monitoring an integrated circuit

The invention relates to a method of resetting a processor, the method comprising the receiving of a reset signal indicating that one or more parts of said processor need to be reset, and forwarding of said reset signal to said parts to be reset. The forwarding of the reset signal is delayed for a period of time for at least one of the parts to be reset. The clock frequency of at least one of the parts to be reset is gradually decreased during said period of time. In this way the total activity of the processor device is gradually decreased so as to avoid an on-chip voltage overshoot, which could cause a total reset of all the parts of the processor.

Systems and methods of resetting a processor

A reset state control circuit adapted to reset independent device domains of an electronic device, said reset state control circuit comprising a capturing unit adapted to capture reset events; and a reset shaping logic adapted to change dynamically a reset control flow to reset device domains of said electronic device depending on a sequence of the reset events captured by said capturing unit.

Method for resetting an electronic device having independent device domains

A system on chip comprises a responder unit comprising a set of responder elements and an access control unit associated with an authorization list and the responder unit. An entry of the authorization list defines a set of access requirements in relation to an address space identifying at least part of the responder unit. The access control unit is arranged to: receive a request for access to a target responder element among the responder elements of the responder unit, determine the corresponding set of access requirements for the received access request from the authorization list, and evaluate the request for access with respect to the determined set of access requirements and generate a first request evaluation result. A protection unit associated with the responder unit is arranged to: provide a group assignment assigning a group to each of the responder elements of the responder unit, provide a group authorization list, an entry of the group authorization list defining a set of group access requirements for the group assigned, receive the request for access to the target responder element, determine the group assigned to the target responder element from the group assignment and further determine the set of group access requirements from the group authorization list for the group assigned. The system-on-chip also evaluates the request with respect to the determined set of group access requirements and generates a second request evaluation result. Interaction with the target responder element is controlled in response to the first and/or second evaluation result.

System on chip and method therefor

A microprocessor comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event, determine if at least one reset condition has been met upon detection of the reset event, and cause at least a part of the microprocessor to remain in a reset state upon determining that the at least one reset condition has been met.

Microprocessor, and method of managing reset events therefor

Transistor-based semiconductor devices, such as systems on chips, may be supplemented with a reset request mechanism to prevent a reset from causing the semiconductor device to enter into an uncertain, or fail, state. More particularly, a method or mechanism may modify a requested reset for a semiconductor device based on a state of the semiconductor device to prevent the semiconductor device from entering an uncertain, an undesired, or a failed state when the reset is effected with regard to the semiconductor device.

Method and device for reset modification based on system state

A method for managing a reset process in a processing system is provided. The method includes enabling a watch dog unit based on a power-on reset (POR) event. A stuck in reset condition indication is received at the watch dog unit and used to determine whether the received reset condition indication corresponds to an unintentional reset condition. If the received reset condition indication is an indication of an unintentional reset condition, a watch dog POR trigger signal is generated and a reset state machine is repeated for system recovery.

Systems and methods for managing reset

A microprocessor device comprises at least one reset management module. The at least one reset management module is arranged to detect a reset event comprising a first reset level, determine if at least one reset condition has been met upon detection of the reset event comprising the first reset level, and cause a reset of a second reset level upon determining that the at least one reset condition has been met.

Microprocessor device, and method of managing reset events therefor

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Oberbergkirchen, Germany

Thomas Henry Luedeke