International Business Machines Corporation

Thomas Helmut Toifl

Christian I Menolfi

Martin L Schmatz

Pier Andrea Francese

Lukas Kull

Marcel A Kossel

Hayden C Cranford, Jr

Giovanni Cherubini

Roy Daron Cideciyan

Alessandro Cevrero

Ilter Özkaya

Daniel Joseph Friedman

John Francis Bulzacchelli

Christoph Hermann Hagleitner

Troy James Beukema

Mounir Meghelli

Simeon Furrer

Thomas E Morf

Jonas R Weiss

Yong Liu

Hazar Yüksel

Gautam Gangasani

Evangelos Stavros Eleftheriou

Abu Sebastian

Michael Anthony Sorna

Manuel Le Gallo-Bourdeau

Glen Arthur Wiedemeier

Ankur Agrawal

Mitch Gusat

Peter L Buchmann

Riduan Khaddam-Aljameh

Danny Chen-Hsien Luu

Hazar Yueksel

Juergen Hertle

Methods and apparatus are provided for training an artificial neural network having a succession of neuron layers with interposed synaptic layers each having a respective set of N-bit fixed-point weights {w} for weighting signals propagated between its adjacent neuron layers, via an iterative cycle of signal propagation and weight-update calculation operations. Such a method includes, for each synaptic layer, storing a plurality p of the least-significant bits of each N-bit weight w in digital memory, and storing the next n-bit portion of each weight w in an analog multiply-accumulate unit comprising an array of digital memory elements. Each digital memory element comprises n binary memory cells for storing respective bits of the n-bit portion of a weight, where n&#x2265;1 and (p+n+m)=N where m&#x2265;0 corresponds to a defined number of most-significant zero bits in weights of the synaptic layer.

Training of artificial neural networks

A system and method for a high-speed transmitter comprising a precoder configured to receive a sequence of input symbols and to generate for each received symbol a respective recoded symbol is disclosed. The transmitter includes a recoding unit configured for recoding each current received PAM-M based on the recoded symbol immediately preceding the current recoded symbol at the recoding unit, a shift unit configured for determining a shift value for each current received symbol from the recoding unit based on the symbol received from the recoding unit and immediately preceding the current symbol at the shift unit; and Feed-Forward Equalizer unit for applying the shift values to the respective symbols received from the recoding unit to generate a corresponding sequence of output symbols to be transmitted in an output stream.

PAM-4 transmitter precoder for 1+0.5D PR channels

An electrostatic discharge (ESD) protection circuit for providing ESD protection to an ESD protected circuit. The protection circuit comprises a signal pad and a crossover network for separating wanted electrical data signals and ESD signals according to their frequency. The protection circuit further comprises a first branch configured to transmit at least a spectral part of the wanted electrical data signals between the signal pad and the ESD protected circuit and a second branch configured to receive the ESD signals from the signal pad. Additionally there is provided a corresponding method, a corresponding integrated circuit chip and a corresponding design structure.

ESD protection circuit

Sequence detectors and detection methods are provided for detecting symbol values corresponding to a sequence of input samples obtained from an ISI channel. The sequence detector comprises a branch metric unit (BMU) and a path metric unit (PMU). The BMU, which comprises an initial set of pipeline stages, is adapted to calculate, for each input sample, branch metrics for respective possible transitions between states of a trellis. To calculate these branch metrics, the BMU selects hypothesized input values, each dependent on a possible symbol value for the input sample and L&#x3e;0 previous symbol values corresponding to possible transitions between states of the trellis. The BMU then calculates differences between the input sample and each hypothesized input value. The BMU compares these differences and selects, as the branch metric for each possible transition, an optimum difference in dependence on a predetermined state in a survivor path through the trellis.

Sequence detectors

A bang-bang phase detector includes set-reset latch, pulse generator, flip-flop, and pulse-width extension circuits. The set-reset latch circuit has set and reset inputs receiving input signals, and a latch output providing a latch output signal whose state varies in dependence on phases of the input signals. The pulse generator circuit generates sampling pulses at timings dependent on phase of an input signal. The flip-flop circuit has a data input, a clock input connected to the pulse generator circuit receiving the sampling pulses, and an output providing a detector output signal whose state distinguishes positive and negative phase differences between input signals. The pulse-width extension circuit connects between the latch output and data input of the flip-flop circuit, and extends width of pulses of a polarity in the latch output signal to extend range of input signal phase differences over which the detector output signal distinguishes positive and negative phase differences.

Bang-bang phase detectors

Embodiments describe a transadmittance amplifier comprising an inverting output port and a non-inverting output port. The transadmittance amplifier comprising a first differential transistor pair having a first transistor comprising an inverting input port. The first transistor is configured to provide an output current to the inverting output port. A second transistor comprising a non-inverting input port. The second transistor is configured to provide an output current to the non-inverting output port. A second differential transistor pair having a third transistor comprising an inverting input port and a fourth transistor comprising a non-inverting input port. A first current source and a second current source. The transadmittance amplifier comprises a first current mirror which is configured to mirror an output current of the fourth transistor to the inverting output port and a second current mirror which is configured to mirror an output current of the third transistor to the non-inverting output port.

Transadmittance amplifier

A sequence detector is provided for detecting symbol values corresponding to a sequence of input samples obtained from a transmission channel. The sequence detector comprises a branch metric unit (BMU), a path metric unit (PMU) and a survivor memory unit. The branch metric unit calculates branch metrics for respective possible transitions between states of a trellis. The path metric unit accumulates branch metrics provided by the branch metric unit in order to establish path metrics. The survivor memory unit selects a survivor path based on the path metrics and outputs a survivor sequence of the detected symbols corresponding to the survivor path. The sequence detector is configured such that the synchronization length is different than the survivor path memory length.

Sequence detector

Embodiments of the present invention may provide improved handling of communication characteristics, such as burstiness, latency-sensitive applications, bandwidth-sensitive applications, etc., to improve peak performance while not compromising other characteristics, such as thermal design power of the input/output chip packages. In an embodiment, in a control circuit that may be connected to and control a data transmitter, a method of transmitting data in a network may comprise receiving at least one feed-forward signal from the data transmitter, receiving at least one feedback signal from at least a first node of the network, comparing the at least one feed-forward signal with at least one threshold or condition, comparing the at least one feedback signal with at least one threshold or condition, and generating a signal indicating that a burst transmission should be started or stopped.

Turbolink: method and apparatus for controlling input/output signaling speed

Octagonal phase rotator apparatus is provided for producing an output signal that is phase dependent on a digital control code. The apparatus includes an I-mixer, a Q-mixer, and first and second IQ-mixers. The I-mixer is responsive to I-control bits of the digital control code. The Q-mixer is responsive to Q-control bits of the digital control code. The first and second IQ-mixers are respectively responsive to one or more IQ1-control bits and one or more IQ2-control bits of the digital control code. The I-mixer comprises an I-DAC for steering current between a positive phase IP and a negative phase IN of an in-phase (I) signal wherein the one or more I-control bits control switching of a first current unit between IP and IN, and a set of amplifiers for weighting the phases IP and IN, in dependence on current steered to each phase by the I-DAC, to produce a weighted I-signal.

Octagonal phase rotators

The exemplary embodiments relate to an asynchronously clocked successive approximation register analog-to-digital converter (SAR ADC) configured to provide a digital approximation of a sampled input signal as a result of an asynchronous successive approximation operation. The converter includes a regulation circuit configured to determine whether the asynchronous successive approximation operation was performed within a predefined conversion time and to regulate the SAR ADC such that the conversion time of the asynchronous operation is shifted towards the predefined conversion time. The embodiments further relate to a corresponding method and a corresponding design structure.

Asynchronously clocked successive approximation register analog-to-digital converter

A zero-crossing amplifier unit for use in high speed analog-digital-converters. A gain stage compares a sampling voltage at an input node with a provided threshold voltage to obtain a gain stage output signal. A voltage controlled current source provides a load current depending on a time window between an initial slope and an end slope of the gain stage output signal. A slope control means increases a duration of a rise and/or fall time of at least one of the initial and end slopes of the gain stage output signal.

Dynamic current source for zero-crossing amplifier units for use in high-speed communication circuits

A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Growing community of inventors

Zurich, Switzerland

Thomas Helmut Toifl