Infineon Technologies Ag

Qimonda Ag

Thomas Hecht

Stefan Jakschik

Matthias Goldbach

Harald Seidl

Martin Gutsche

Uwe Schröder

Bernhard Sell

Albert Birner

Stephan Kudelka

Andreas Orth

Uwe Schroeder

Jörn Lützen

Annette Saenger

Christian Kapteyn

Thomas Mikolajick

Dirk Manger

Michael Stadtmueller

Matthias Foerster

Ulrich Mantz

Lars Heineck

Henry Bernhardt

J&ouml;rn L&uuml;tzen

Uwe Paul Schr&ouml;der

Matthias Schmeide

Matthias Leonhardt

Alejandro Avellan

A gate electrode structure comprises at least one bi-layer, wherein each bi-layer comprises a plating film and a stress amplifier film. The plating film includes a poly-crystalline material. The stress amplifier film determines the crystallization result of the poly-crystalline material, wherein a mechanical stress induced through the plating layer is amplified. Tensile or compressive strain may be induced in a crystalline substrate. Electron or hole mobility may be increased and on-resistance characteristics of a MOS field effect transistor may be improved.

Gate electrode structure, MOS field effect transistors and methods of manufacturing the same

An electrical component, such as a DRAM semiconductor memory or a field-effect transistor is fabricated. At least one capacitor having a dielectric () and at least one connection electrode () are fabricated. To enable the capacitors fabricated to have optimum storage properties even for very small capacitor structures, the dielectric () or the connection electrode () are formed in such a manner that transient polarization effects are prevented or at least reduced.

Method for fabricating an electrical component

The present invention relates to a method of fabricating a capacitor in a semiconductor substrate. The capacitor is fabricated such that the capacitor comprises: a trench inside a substrate, the trench having a lower region and an upper region, wherein the trench's diameters in the lower region is larger than in the upper region; a first electrode; a dielectric layer on top of the first electrode; a conductive layer on top of the electric layer, the conductive layer forming a second electrode of the capacitor; and a plug forming a closed cavity inside the lower region.

Method for fabricating a capacitor

The present invention provides a coating process for patterned substrate surfaces, in which a substrate () is provided, the substrate having a surface () which is patterned in a substrate patterning region () and has one or more trenches () that are to be filled to a predetermined filling height (), a catalyst layer () is introduced into the trenches () that are to be filled, a reaction layer () is deposited catalytically in the trenches () that are to be filled, the catalytically deposited reaction layer () is densified in the trenches () that are to be filled, and the introduction of the catalyst layer () and the catalytic deposition of the reaction layer () are repeated until the trenches () that are to be filled have been filled to the predetermined filling height ().

Coating process for patterned substrate surfaces

On a substrate surface, which has been patterned in the form of a relief, of a substrate, typically of a semiconductor wafer, a deposition process is used to provide a covering layer on process surfaces which are vertical or inclined with respect to the substrate surface. The covering layer is patterned in a direction which is vertical with respect to the substrate surface by limiting a process quantity of at least one precursor material and/or by temporarily limiting the deposition process, and is formed as a functional layer or mask for subsequent process steps.

Process for vertically patterning substrates in semiconductor process technology by means of inconformal deposition

The present invention relates to a method for determining the depth of a buried structure in a semiconductor wafer. According to the invention, the layer behavior of the semiconductor wafer which is brought about by the buried structure when the semiconductor wafer is irradiated with electromagnetic radiation in the infrared range and arises as a result of the significantly longer wavelengths of the radiation used in comparison with the lateral dimensions of the buried structure is utilized to determine the depth of the buried structure by spectrometric and/or ellipsometric methods.

Method for determining the depth of a buried structure

Integrated circuit device comprising a conductive layer and a poly-crystalline silicon layer, wherein the integrated circuit device further comprises an intermediate counter-stress layer. This intermediate counter-stress layer is arranged between the poly-crystalline silicon layer and the conductive layer, and enables stress-reduced crystallization of the poly-crystalline silicon layer. Further, the intermediate counter-stress layer is amorphous at and below a poly-silicon crystallization temperature.

Method for fabricating an integrated circuit on a semiconductor substrate

A process for modifying sections of a semiconductor includes covering the sections to remain free of doping with a metal oxide, e.g., aluminum oxide. Then, the semiconductor is doped, for example, from the gas phase, in those sections that are not covered by the aluminum oxide. Finally, the aluminum oxide is selectively removed again, for example using hot phosphoric acid. Sections of the semiconductor surface which are formed from silicon, silicon oxide or silicon nitride remain in place on the wafer.

Method for fabricating microchips using metal oxide masks

A method for producing a dielectric layer on a substrate made of a conductive substrate material includes reducing a leakage current that flows through defects of the dielectric layer at least by a self-aligning and self-limiting electrochemical conversion of the conductive substrate material into a nonconductive substrate follow-up material in sections of the substrate that are adjacent to the defects. Also provided is a configuration including a dielectric layer with defects, a substrate made of a conductive substrate material, and reinforcement regions made of the nonconductive substrate follow-up material in sections adjacent to the defects.

Method and configuration for reinforcement of a dielectric layer at defects by self-aligning and self-limiting electrochemical conversion of a substrate material

A dielectric barrier layer composed of a metal oxide is applied in thin layers with a thickness of less than 20 nanometers in the course of processing semiconductor devices by sequential gas phase deposition or molecular beam epitaxy in molecular individual layers on differently structured base substrates. The method allows, inter alias, effective conductive diffusion barriers to be formed from a dielectric material, an optimization of the layer thickness of the barrier layer, an increase in the temperature budget for subsequent process steps, and a reduction in the effort for removing the temporary barrier layers.

Barrier layer and a method for suppressing diffusion processes during the production of semiconductor devices

The invention provides a method for fabricating a memory cell, a substrate () being provided, a trench-type depression () being etched into the substrate (), a barrier layer () being deposited non-conformally in the trench-type depression (), grain elements () being grown on the inner areas of the trench-type depression (), a dielectric layer () being deposited on the surfaces of the grain elements and the inner areas of the trench-type depression, and a conduction layer being deposited on the dielectric layer, the grain elements () growing selectively on the inner areas () of the trench-type depression () in an electrode region () forming a lower region of the trench-type depression () and an amorphous silicon layer continuing to grow in a collar region () forming an upper region of the trench-type depression ().

Memory cell and method for fabricating it

Charge-trapping regions are arranged beneath lower edges of the gate electrode separate from one another. Source/drain regions are formed in self-aligned manner with respect to the charge-trapping regions by means of a doping process at low energy in order to form shallow junctions laterally extending only a small distance beneath the charge-trapping regions. The self-alignment ensures a large number of program-erase cycles with high effectiveness and good data retention, because the locations of the injections of charge carriers of opposite signs are narrowly and exactly defined.

Charge-trapping memory device and method of production

A method for fabricating patterned ceramic layers on areas of a relief structure, wherein the layers may be arranged essentially perpendicular to a top side of a substrate. In exemplary embodiments, a patterned ceramic layer forms an oxide collar for a trench capacitor. The oxide collar is produced by a trench firstly being filled with a resist in its lower section, and an oxide layer subsequently being produced on the uncovered areas of the substrate with the aid of a low temperature ALD method. By means of anisotropic etching, only those portions of the ceramic layer which are arranged at the perpendicular walls of the trench remain. The resist filling may subsequently be removed, for example, by means of an oxygen plasma.

Method of fabricating an oxide collar for a trench capacitor

A structure on a layer surface of the semiconductor wafer has at least one first area region (), which is reflective for electromagnetic radiation, and at least one second, essentially nonreflecting area region (). A light-transmissive insulation layer () and a light-sensitive layer are produced on said layer surface. The electromagnetic radiation is directed onto the light-sensitive layer with an angle &#x398; of incidence and the structure of the layer surface is imaged with a lateral offset into the light-sensitive layer.

Method for the production of a self-adjusted structure on a semiconductor wafer

The invention relates to a method for production of a metallic or metal-containing layer () by using a pre-cursor on a silicon- or germanium-containing layer, of, in particular, an electronic component, whereby an intermediate layer is applied to the silicon- or germanium-containing layer before the use of the pre-cursor. Said intermediate layer forms a diffusion barrier for at least those elements or the pre-cursor which would etch the silicon- or germanium-containing layer and is itself resistant to etching by the pre-cursor.

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Dresden, Germany

Thomas Hecht