Advanced Micro Devices Corporation

Thomas H Wong

John W Chu

Mei Hsu

An adjustable sense amplifier circuit for read/write control of solid state memory devices is described. In a write mode the circuit includes a write select path, coupled to a current source and coupled to a differential pair of data select transistors, wherein the input data state sets each of two differential pairs formed by the memory element cross-coupled latch, such that the memory element stores selected data. In a sense mode, a second current path is selected wherein an adjustable sense level is provided to each of two differential pairs formed by the memory element. The current source is coupled to a reference voltage source which is independent of the supply voltage. The reference voltage source tracks changes in temperature and also provides low beta compensation for current loss due to the low beta value of transistors in the write and sense paths.

Sense amplifier/write circuit for semiconductor memories

An emitter coupled gate circuit for providing both a full output voltage swing and a fractional output voltage swing with an adjustable high level output voltage includes a single differential transistor circuit having a first current switch transistor and a second current switch transistor and a single constant-current source. A first load resistor has its one end connected operatively to the collector of the second current switch transistor. A second load resistor has its one end connected operatively to the collector of the second current switch transistor, and a level shifting resistor has its one end connected to the other end of the second load resistor. A first emitter follower transistor has its base connected to the one end of the first load resistor and its emitter connected to an upper-level full output voltage swing terminal. A second emitter follower transistor has its base connected to the one end of the second load resistor and its emitter connected to an upper-level fractional output voltage swing terminal. The upper-level fractional output voltage swing terminal has an adjustable high level output voltage which is controlled by the ratios of the resistance values of the level shifting resistor relative to the first load resistor and the second load resistor.

Full and fractional swing with adjustable high level ECL gate using a

A dual bus driver including a voltage input, a current source, a single data input, a first driver transistor for driving one bus, a second driver transistor for driving the other bus, a first pair of differential transistors for turning on either the first driver transistor or the second driver transistor to couple an input signal at the data input to the one bus or the other bus, and a second pair of differential transistors for disabling both driver transistors. By providing a driver that drives both buses, reduced power consumption, fewer circuit components and less integrated circuit layout complexities are achieved.

Apparatus for driving first and second devices

A reference voltage generator including a circuit for generating a reference voltage V.sub.REF having a non-linear voltage-temperature function, in which the improvement comprises an additional resistor being in circuit to make the function linear. By making the function linear, the equation defining V.sub.REF is easily differentiated to determine the change in voltage with temperature.

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Sunnyvale, CA, United States of America

Thomas H Wong