Xilinx, Inc.

Thomas H Strader

Wayne Edward Wennekamp

Schuyler E Shimanek

Adam Elkins

Roger D Flateau, Jr

Steven E McNeil

Ephrem C Wu

James M Simkins

Matthew H Klein

Chidamber Kulkarni

Hongbin Ji

James E Ogden

Subodh Kumar

Uma E Durairajan

Mikhail A Wolf

Joe E Leyba

Steven E Mcneil

Kumar Subodh

Adam Elklns

In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.

Power control over memory cell arrays

An embodiment of a memory module is disclosed. This memory module is a configurable hard macro. A portion of this memory module includes a data input multiplexer coupled to select between cascaded data and direct/bused data. Such portion further includes, a memory coupled to receive output from the data input multiplexer for storage therein, and a register input multiplexer coupled to select between read data from the memory and the cascaded data. This memory module further includes: a register coupled to receive output from the register input multiplexer, a latch/register mode multiplexer coupled to select between the read data from the memory and registered data from the register, and a data output multiplexer coupled to select between the cascaded data and output from the latch/register mode multiplexer to provide output data.

Configurable embedded memory system

A programmable integrated circuit device (IC) can include a configuration controller configured to assert a suspend request signal responsive to an input triggering suspend mode within the programmable IC and a memory controller block coupled to the configuration controller and a memory device. The memory controller block can be configured to place the memory device in self refresh mode in response to the suspend request signal and assert a suspend acknowledgement signal subsequent to placing the memory device in self refresh mode. The configuration controller can continue implementing suspend mode within the programmable IC in response to assertion of the suspend acknowledgement signal.

Memory controller with suspend feature

An embodiment of a technique to transfer data includes: operating a memory interface using memory access cycles that each include T successive time slots each provided for transfer of B bits of data, where T and B are positive integers; selecting one of first or second predetermined integers as one of T or B; and transferring a quantity of data Q between the memory interface and another interface. The transferring includes: automatically determining a value of M memory access cycles as a function of the one of T or B; causing a data transfer sequence on the memory interface that includes M successive memory access cycles and thus M&#xb7;T time slots; automatically determining a subset of the M&#xb7;T time slots as a function of the one of T or B; and transferring the quantity of data Q through the memory interface during the subset of time slots.

Method and apparatus for transferring data to or from a memory

A technique is provided for memory control in a device having programmable circuitry, including providing a dedicated memory controller circuit in the device before the programmable circuitry is field programmed. Another technique involves fabricating a device, where the fabricating involves forming programmable circuitry that includes a dedicated memory controller circuit before the circuitry is field programmed.

Method and apparatus for memory control with a programmable device

A device has first circuitry and also second circuitry that includes an interface and command ports that can each receive commands from the first circuitry, each command requesting an information transfer through the interface. A technique relating to the device involves dynamically enabling and disabling at least one of the command ports under control of the first circuitry, and using a priority list specifying an order of priority for a group of the command ports to identify and cause a command to be accepted from the command port of highest priority that contains a command and is currently enabled.

Method and apparatus for arbitration among multiple ports

An apparatus includes a programmable device that has an interface and command ports that can each receive commands, each command requesting an information transfer through the interface. A technique relating to the device involves: selecting during field programming a number of priority definitions; configuring each of the priority definitions during field programming to specify an order of priority for a group of the command ports; and using the priority definitions in succession and, for each of the priority definitions, causing a command to be accepted from the command port of highest priority that contains a command.

Method and apparatus for multi-port arbitration using multiple time slots

A technique is applicable to a device having programmable circuitry that includes a first interface having a plurality of first address terminals, a second interface having a plurality of second address terminals, and a configurable interconnect structure coupled between the first and second interfaces. The technique includes configuring the interconnect structure during field programming to electrically couple each of the address terminals in a first subset of the first address terminals to respective address terminals in a second subset of the second address terminals according to a selected one of a plurality of different mapping functions.

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San Jose, CA, United States of America

Thomas H Strader