Matrix Semiconductor, Inc.

Rambus Inc.

Sandisk 3D LLC

Leland Stanford Junior University

Zerog Wireless, Inc.

Other

Sandisk Technologies Inc.

Advanced Micro Devices Corporation

Microchip Technology Inc.

Kabushiki Kaisha Toshiba

Sandisk Corporation

Clark-Reliance Corporation

Thomas H Lee

Mark G Johnson

James Montague Cleeves

Vivek Subramanian

Paul Michael Farmwald

Kevin S Donnelly

Bendik Kleveland

Tsyr-Chyang Ho

Mark A Horowitz

Bruno Werner Garlepp

Pak Shing Chau

Jun Y Kim

Yiu-Fai Chan

P Michael Farmwald

Stanley Wang

Igor G Kouznetzov

Donald C Stark

Benedict C Lau

Igor G Kouznetsov

Leung Yu

Chanh Vi Tran

Christopher John Petti

Andrew J Walker

Nhat M Nguyen

Roy E Scheuerlein

Jared L Zerbe

N Johan Knall

J James Tringali

Derek Bosch

Matthew P Crowley

Clemenz L Portmann

Brad Herner

Arvin R Shahani

Hirad Samavati

Steven Walther

Derek K Shaeffer

Luca Giovanni Fasoli

Shinobu Fujita

Wayne S Richardson

Alper Ilkbahar

Ramin Farjad-Rad

John Christian Holst

Dickson T Wong

Chaofeng Huang

Grace Tsang

Stephen P Boyd

Arthur J Collmeyer

Donald C Cox

Maria Del Mar Hershenson

Mehdi Frederik Soltan

Mark A Colman

Andy Chan

Joel L Dawson

Susan Luschas

Yuen Hui Chee

K Derek Shaeffer

Theresa H Meng

Sydney Reader

James M Cleeves

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.

Dense arrays and charge storage devices

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive levels is planarized by chemical mechanical polishing.

A three-dimensional memory is provided that includes a first memory level and a second memory level monolithically formed above the first memory level. The first memory level includes a first steering element coupled in series with and vertically stacked above or below a first non-volatile state change element. The second memory level includes a second steering element coupled in series with and vertically stacked above or below a second non-volatile state change element. Other aspects are also provided.

Three-dimensional nonvolatile memory and method of fabrication

A pillar-shaped memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. Other aspects are also provided.

Pillar-shaped nonvolatile memory and method of fabrication

A memory cell is provided that includes a steering element, and a non-volatile state change element coupled in series with the steering element. The steering element and state change element are disposed in a vertically-oriented pillar. Other aspects are also provided.

Vertically stacked field programmable nonvolatile memory and method of fabrication

A memory cell is provided that includes a first conductor, a second conductor, a steering element that is capable of providing substantially unidirectional current flow, and a state change element coupled in series with the steering element. The state change element is capable of retaining a programmed state, and the steering element and state change element are vertically aligned with one another. Other aspects are also provided.

A hybrid circuit () for use with communications transceivers. The hybrid circuit () combines the function of an ESD protection circuit () with the function of a TX/RX switch (). The input node of the hybrid circuit () is connecting between the source of an ESD event () and a device to be protected (). The hybrid circuit () includes an ESD protection element (), which is triggered by a triggering transistor (). The gate of the triggering transistor () is connected to a driver () for turning the triggering transistor () on during transmission and for turning the triggering transistor () off during reception.

Hybrid circuit for circuit protection and switching

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. Maximum use of self alignment techniques minimizes photolithographic limitations. In one embodiment the peripheral circuits are formed in a silicon substrate and an N level array is fabricated above the substrate.

Integrated circuit incorporating decoders disposed beneath memory arrays

Three terminal nonvolatile memory device with vertical gated diode

A calibration circuit () and method () for calibrating the bias current of a VCO () to minimize phase noise. The calibration circuit () monitors the average voltage at the common-mode node of the VCO () while varying the bias current over a predetermined range. The calibration circuit () identifies the bias current associated with the minimum average common-mode voltage and utilizes this bias current for calibrating the biasing transistor of the VCO ().

Calibration of voltage controlled oscillators

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Cupertino, CA, United States of America

Thomas H Lee