Advanced Micro Devices Corporation

Other

Thomas H Hamilton

Kevin M Brandl

Shawn Searles

James Raymond Magro

Kedarnath Balakrishnan

Mark Fowler

Tahsin Askar

Guanhao Shen

Oswin E Housty

Michael J Stephenson

Hideki Kanayama

Robert S Eby

Robert G Harteker

Deborah H Andrews

A system includes a memory system comprising a memory module and a processor adapted to access the memory module using a memory controller that includes a controller having an input for receiving a power state change request signal and an output for providing memory operations, and a memory operation array comprising a plurality of entries. Each entry includes a plurality of encoded fields. The memory operation array is programmable to store different sequences of commands for particular types of memory of a plurality of types of memory in the plurality of entries that initiate entry into and exit from supported low power modes for the particular types of memory. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the at least one entry.

Self refresh state machine mop array

A memory controller includes a host interface for receiving memory access requests including access addresses, a memory interface for providing memory accesses to a memory system, and an address decoder coupled to the host interface for programmably mapping the access addresses to selected ones of a plurality of regions. The address decoder is programmable to map the access addresses to a first region having a non-power-of-two size using a primary decoder and a secondary decoder each having power-of-two sizes, and providing a first region mapping signal in response. A command queue stores the memory access requests and region mapping signals. An arbiter picks the memory access requests from the command queue based on a plurality of criteria, which are evaluated based in part on the region mapping signals, and provides corresponding memory accesses to the memory interface in response.

Memory controller with flexible address decoding

In one form, a memory controller includes a controller and a memory operation array. The controller has an input for receiving a power state change request signal and an output for providing memory operations. The memory operation array comprises a plurality of entries, each entry comprising a plurality of encoded fields. The controller is responsive to an activation of the power state change request signal to access the memory operation array to fetch at least one entry, and to issue at least one memory operation indicated by the entry. In another form, a system comprises a memory system and a processor coupled to the memory system. The processor is adapted to access the memory module using such a memory controller.

Self refresh state machine MOP array

Timing delays in a double data rate (DDR) dynamic random access memory (DRAM) controller () are trained. A left edge of passing receive enable delay values is determined (). A final value of a receive data strobe delay value and a final value of a transmit data delay value are trained (). A right edge of passing receive enable delay values is determined using a working value of the receive data strobe delay (); and a final receive enable delay value intermediate between the left edge of passing receive enable delay values and the right edge of passing receive enable delay values is set ().

Method for training dynamic random access memory (DRAM) controller timing delays

Methods and apparatus are provided for use in testing a memory () coupled to a processing node (). A background scrubber () in the processing node () is initialized to perform a test of the memory (). A status of the background scrubber () is checked in which the status indicates whether an error occurred during the test. A predetermined action is taken in response to the status indicating that the error occurred during the test.

Efficient memory check architecture and method

In response to a cold reset in a computer system, a plurality of indications in a nonvolatile memory are initialized to a first state. Each of the plurality of indications is assigned to a respective one of a plurality of tasks to be executed on one or more processors of the computer system. A first task of the plurality of tasks is executed, including changing a first indication of the plurality of indications to a second state, wherein the first indication is assigned to the first task. A computer accessible medium comprising one or more instructions implementing the initialization and one or more instructions comprise the first task is also contemplated, as well as a computer system including a processor and the computer accessible medium.

Facilitating cold reset and warm reset tasking in a computer system

A technique for initializing a memory controller of a plurality of memory modules for optimum system performance is presented. A plurality of optimum sets of operational parameters that are supported by the memory controller and the plurality of memory modules are determined. A plurality of benchmark calculations using the plurality of optimum sets of operational parameters produces a plurality of benchmark numbers. The memory controller is configured with the one of the plurality of optimum sets of operational parameters that produces the best of the plurality of benchmark numbers. The benchmark calculations can be based on a variety of conditions, for example, burst length or the minimum time to read a random row of memory. Additionally, the benchmark calculations can be weighted in favor of frequency.

Firmware algorithm for initializing memory modules for optimum performance

The invention is a UF.sub.6 -recovery process of the kind in which a stream of substantially pure gaseous UF.sub.6 is directed through an externally chilled desublimer to convert the UF.sub.6 directly to an annular solid ring adhering to the interior wall of the desublimer. After accumulation of a desired amount of solid UF.sub.6, the desublimer is heated to liquefy the solid. Subsequently, the liquid is recovered from the desublimer. It has been found that during the heating operation the desublimer is subjected to excessive mechanical stresses. In addition, it has been found that the incorporation of a very small percentage of relatively noncondensable, nonreactive gas (e.g., nitrogen) in the UF.sub.6 input to the desublimer effects significant decreases in the stresses generated during the subsequent melting operation. This modification to the process provides valuable advantages in terms of reduced hazard, lower operating costs for the desublimer, and increased service life for the desublimer and its auxiliaries. The new process is especially suitable for the recovery of enriched UF.sub.6 from high-speed UF.sub.6 gas-centrifuge cascades.

Growing community of inventors

Pflugerville, TX, United States of America

Thomas H Hamilton