Rambus Inc.

Mellanox Technologies, Ltd.

Velio Communications, Inc.

Rumbus Inc.

Thomas H Greer, Iii

John Wood Poulton

Hae-Chang Lee

Ramin Farjad-Rad

William James Dally

Brian S Leibowitz

Jade M Kizer

Teva J Stone

Hiok-Tiaq Ng

Mark A Horowitz

Robert E Palmer

Stephen G Tell

Akash Bansal

Jaeha Kim

John Eble

Segev Zarkovsky

A receiver includes a continuous-time equalizer, a decision-feedback equalizer (DFE), data and error sampling logic, and an adaptation engine. The receiver corrects for inter-symbol interference (ISI) associated with the most recent data symbol (first post cursor ISI) by establishing appropriate equalization settings for the continuous-time equalizer based upon a measure of the first-post-cursor ISI.

High-speed signaling systems and methods with adaptable, continuous-time equalization

A system comprises a transmitter that generates a combined signal including a first group of optical signals and a second group of optical signals, the first group of optical signals comprising M+X number of optical signals in a first polarization mode, the second group of optical signals comprising N number of optical signals in a second polarization mode, wherein the number of N and M optical signals comprise payload signals, where the X number of optical signals comprises at least one first pilot signal. The system may further include a receiver comprising a polarization recovery device that receives the combined signal and that recovers, from the combined signal, the first group of optical signals with the first polarization mode and the second group optical signals with the second polarization mode based on feedback indicative of at least one signal characteristic of the at least one first pilot signal.

Systems, devices, and methods for dual polarization recovery

A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the frequency offset, or rate of change of the frequency offset, between an arriving signal and the recovered clock signal.

Clock and data recovery using receiver clock spread spectrum modulation and offset compensation

A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signal according to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock.

A system and method for performing clock and data recovery. The system sets the phase of a recovered clock signalaccording to at least three estimates of the rate of change of an offset between the frequency of the data transmitter clock and the frequency of a receiver clock

Clock and data recovery employing piece-wise estimation on the derivative of the frequency

A circuit to test phase linearity of a phase synthesizer, which synthesizes an output clock having a phase corresponding to a digital phase value input to the phase synthesizer. A digital counter provides the digital phase value to the phase synthesizer. The digital counter receives a counter clock synchronized with an input clock. The digital phase value is stepped by the digital counter, thereby shifting the frequency of the output clock. The output clock is analyzed with respect to phase linearity of the phase synthesizer to produce a phase linearity analysis output.

Hardware and method to test phase linearity of phase synthesizer

A phase controller can be part of a phase-locked loop (PLL) or a delay-locked loop (DLL). The phase controller includes first and second regulators. The first regulator provides power supply noise rejection while the second regulator provides phase and frequency lock.

Power supply noise rejection in PLL or DLL circuits

A processor-controlled clock-data recovery (CDR) system. Phase error signals having either a first state or a second state are generated within the CDR system according to whether a first clock signal leads or lags transitions of a data signal. A difference value is generated based on the phase error signals, the difference value indicating a difference between the number of the phase error signals having the first state and a number of the phase error signals having the second state. The difference value is transferred to a processor which is programmed to determine whether the difference value exceeds a first threshold and, if so, to adjust the phase of the first clock signal.

Processor-controlled clock-data recovery

An oscillating signal in an oscillator is caused to phase shift toward the phase of an input signal coupled to the oscillating signal. The resonant frequency of the oscillator is about equal to an integer multiple of the frequency of the input signal. The input signal may be generated in a pulse generator to have an input pulse duration less than or equal to that of the oscillating signal. The oscillator circuit may be used as a filter to filter pulse width variations or to filter jitter from a reference clock. The oscillator circuit may also serve as a buffer by amplifying the input signal. Phase interpolation can be obtained by coupling at least one input signal with at least one oscillating signal.

Phase controlled oscillator circuit with input signal coupler

A pleisiochronous repeater system and components thereof are disclosed. In one particular exemplary embodiment, a pleisiochronous repeater system component may be realized as a receiver circuit comprising a clock multiplier that multiplies a reference clock signal by an integer multiple to generate a data clock signal. The receiver circuit may also comprise a divider circuit that generates a timing reference signal having a frequency that is not an integer divisor of a frequency of the reference clock signal.

Pleisiochronous repeater system and components thereof

A wide-range multi-phase clock generator having a first clock generating circuit, a frequency divider circuit, and a plurality of multiplexers. The first clock generating circuit generates a plurality of first clock signals, each having a first frequency and a respective one of a plurality of different phase angles. The frequency divider circuit receives the plurality of first clock signals from the first clock generating circuit, and generates a plurality of second clock signals, each having a second frequency and a respective one of the plurality of different phase angles. The multiplexers each have a first input coupled to receive a respective one of the first clock signals and a second input coupled to receive a respective one of the second clock signals having substantially the same phase angle as the one of the first clock signals.

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Chapel Hill, NC, United States of America

Thomas H Greer, Iii