The Boeing Company

Thomas H Friddell

Brian Kenneth Kormanyos

Rodney Kevin Bonebright

Michael J Dunn

An antenna array includes a plurality of power amplifiers, each having a signal input, a signal output coupled to a cell of the antenna array, and a power input. The antenna array includes a plurality of power supplies, each power supply individually and separately coupled to a corresponding one of the plurality of power amplifiers at a respective power input. The antenna array further includes single a pre-distortion linearizer with a linearizer input that receives a signal and a linearizer output that is coupled to each signal input of each of the plurality of power amplifiers. Each power amplifier is operated in gain compression by setting its operating voltage according to a power output of the power amplifier.

Simultaneous linearization of multiple power amplifiers with independent power

Semiconductor devices, systems, and methods are disclosed to facilitate power management. A method includes operating a first voltage range island of a semiconductor device within a first voltage range. The first voltage range includes a first midpoint. The first voltage range is provided in part by a voltage source that includes a tracking voltage regulator. The method also includes operating a second voltage range island of the semiconductor device within a second voltage range. The second voltage range includes a second midpoint. The first voltage range is different than the second voltage range.

System and method of controlling devices operating within different voltage ranges

An active chaff may be released by an aircraft to assist the aircraft in evading at least one of radar detection and a missile. The active chaff may include a signal generator, a signal spreading device, a microprocessor, a power source, and a substantially high-drag aerodynamic envelope. The signal generator may emit a signal to assist the aircraft in evading radar detection and/or a missile. The signal spreading device may spread the generated signal. The microprocessor may control the signal generator and the signal spreading device. The power source may power the signal generator and the microprocessor. Each of the signal generator, signal spreading device, microprocessor, and power source may be located on or within the substantially high-drag aerodynamic envelope.

Active chaff

Semiconductor devices, systems, and methods are disclosed to facilitate power management. A semiconductor device includes a first voltage island configured to operate within a first voltage range, where the first voltage range has a first midpoint. A second voltage island of the semiconductor device is configured to operate within a second voltage range, where the second voltage range has a second midpoint. The first voltage range is different than the second voltage range, and the first midpoint is substantially equal to the second midpoint.

Methods, apparatuses, and systems are disclosed to facilitate power management of asynchronous logic devices to operate asynchronous logic devices at a desired level of processing throughput with minimal power consumption. A plurality of completion signals is received from a processing circuit. Each of the plurality of completion signals identifies an associated operation has been completed by the processing circuit. A plurality of phase signals is generated where the plurality of phase signals includes a respective phase signal generated at a time when each of the plurality of completion signals is expected to be received. A plurality of time differences is determined where each of the time differences is based on a difference between receipt of a completion signal and the respective phase signal generated at the time when the completion signal is expected to be received. A composite difference of the time differences is totaled. A voltage supplied to the processing circuit is adjusted based on the composite difference.

System and method of asynchronous logic power management

A method for reducing fading channel signal data loss for serial data rates up to approximately 10 gigabits per second includes sequentially distributing serial data to multiple encoders. Individual data bytes are sent from the encoders to a convolutional interleaver. Each byte is distributed to an individual memory element of the interleaver in a received byte sequence. An address generator generates write and read addresses assignable to each memory element. Multiple shift registers have variably graduated lengths. The serial data is distributed between channels each having a different delay element created by shift register length differences. The delay elements are adjustable to correct data dropout due to daily atmospheric/channel changes. Fade detection signals are inserted before transmission and measured at a receiver. The fade signals help create erasure bits to improve decoding accuracy and adjust interleaver delay parameters.

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Kent, WA, United States of America

Thomas H Friddell