Motorola Corporation

Other

Dmos Collective, Inc.

Thomas H Bennett

Michael F Wiles

Earl F Carlow

Charles I Peddle

Rodney H Orgill

Anthony E Kouvoussis

William D Mensch, Jr

Edward C Hepworth

Wilbur L Mathys

R Gary Daniels

Fuad H Musa

John Hastings Koehler

Susan Pieper-Bailey

Gene A Schriber

W Bryant Wilder, Jr

William B Wilder, Jr

Shovel

A handheld scooping and shaping device comprising a snow shaping section, a first hollow rigid shaft segment, a plurality of additional hollow rigid shaft segments, and a handle. The snow shaping section comprises a scooping panel, back panel, first sidewall, second sidewall, and bottom panel. The scooping panel comprises a distal end having a plurality of teeth extending outwardly. The back panel opposes the scooping panel. The first sidewall opposes the second sidewall. The bottom panel is coupled or integrated to the scooping panel, back panel, first sidewall and second sidewall. The first hollow rigid shaft segment is removably coupled to the snow shaping section. The plurality of additional hollow rigid shaft segments are configured to nest within at either the first hollow rigid shaft segment or an additional hollow rigid shaft segment. The handle is coupled or integrated to one of the additional hollow rigid shaft segments.

Device, system, and method for shoveling and shaping snow

An apparatus, system, and method are disclosed for controlling movement of a user on snow. The apparatus includes a support member comprising a shaft made from a rigid material, a snow interface, and an engagement member. The snow interface extends from a first end of the shaft and includes a gliding surface opposing a propulsion surface. The engagement member is coupled to one of the gliding surface and the propulsion surface of the snow interface. The snow interface is positionable between a gliding position and a slowing position. In the gliding position, the gliding surface is positioned in contact with a surface of the snow and the engagement member is positioned out of contact with the surface of the snow. In the slowing position the engagement member is positioned in contact with the surface of the snow.

Apparatus, system, and method for controlling movement of a user on snow

A microprocessor on a monolithic integrated circuit is provided having a single clock input pin for receiving a clock input signal. The clock input signal is used to gate address data onto the address bus and to enable a data input dynamic latch. In addition the input clock signal is used to generate two complementary non-overlapping clock signals used for synchronizing purposes within the microprocessor.

Data processor having single clock pin

A digital data processor on a single monolithic integrated circuit chip is provided which uses one less pin. The elimination of the pin is accomplished by using, internally to the processor, a valid memory address signal to gate information from the address but to an address output line. Whenever an address is not present on the address bus all logic '1's' are generated on the address output bus.

Valid memory address pin elimination

A microprocessor comprises an internal address bus having a first portion (2,4) having a plurality of conductors carrying the low order address byte and a second portion (10) having a plurality of conductors for carrying the high order address byte. The microprocessor further comprises a plurality of registers, including an incrementor (12,13), a program counter (14,15), a temporary register (16,17), a stack pointer (18,19), an index register (20,21), and an accumulator (22,24), each comprising a pair of 8-bit registers for temporarily storing information. An arithmetic logic unit (28) performs computational operations on digital information within the microprocessor. The microprocessor includes a pair of internal data buses (6,8) each having a plurality of conductors for conducting digital information within the microprocessor. Means are provided for coupling selected ones of the registers, or the high or low order portions thereof, to the first and second data buses. The provision plural internal data buses permits a greater number of transfers of digital information to occur within the microprocessor during each machine cycle. The result is more efficient microprocessor operation and higher throughput.

Microprocessor having plural internal data buses

A digital system including a plurality of metal-oxide-semiconductor (MOS) chip random access memories (RAM), read only memories (ROM) and peripheral interface adaptors coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU). Each peripheral interface adaptor includes a control register loadable under program control. The contents of the control register control selection of several registers within the interface adaptor. The control register also controls other functions of the peripheral interface adaptor, including determining direction of data movement at the peripheral buffers of the interface adaptor. The contents of the control register of each interface adaptor are monitorable by the microprocessor unit.

Digital data processing system with interface adaptor having

A peripheral interface adaptor (PIA) circuit for data processing systems contains memory elements or control registers allowing modification under program control of the logical functions of the PIA. The peripheral interface adaptor includes a plurality of system data bus buffer circuits coupled to a system data bus and further includes peripheral interface buffer circuits coupled to a bidirectional peripheral data bus. The direction of data flow in the peripheral data bus is controlled by a data direction register. Data from the system data bus buffer is entered into an input register, and is transferred from there to an input bus coupled to the control register, a data direction register and a data register. Data from the peripheral data bus, the data direction register and the control register are transferred via an output bus to the system data bus buffers. Control signals are generated by select, read/write control, and register select logic which provides signals on a control bus coupled to the input register, the data register, the control register, and the data direction register to control data transfers between the various buses, registers, and buffer circuits.

Interface adaptor architecture

A circuit and a method for adding an 8-bit operand to a 16-bit operand are disclosed such that the number of machine cycles required by a data processor to perform such an addition is reduced. The 8-bit operand and the least significant byte of the 16-bit operand are added together within an 8-bit adder circuit to generate the least significant byte of the result. Simultaneously, the most significant byte of the 16-bit operand is stored in a temporary register and is also input to an increment/decrement network. The adder circuit, after a given delay time, generates a carry signal depending on whether a carry-out was produced by the addition. The carry signal and the sign bit of the 8-bit operand control the mode of operation of the increment/decrement network and determine whether the increment/decrement network or the temporary register will be selected to provide the most significant byte of the result.

Carry anticipator circuit and method

An N-channel field effect transistor microprocessor includes an arithmetic logic unit, a plurality of working registers and address generating circuitry coupled to an internal bus. Control circuitry is coupled to the arithmetic logic unit, the working registers, and the address generating circuitry for producing control signals for controlling operation of the arithmetic logic unit, the working registers, and the address generating circuitry. The microprocessor requires only a single external power supply, and includes means connected to the external power supply for providing electrical energy to the working registers, the arithmetic logic unit, the control circuitry, and the address generating circuitry in order to effect operation thereof.

N-channel field effect transistor integrated circuit microprocessor

A digital system includes a microprocessor coupled to a data bus and an address bus. A memory for storing data and instructions is connected to the data bus and the address bus. A peripheral device is connected to an interface adaptor. The interface adaptor is connected to the data bus and the address bus, and performs the function of interfacing between the digital system and a peripheral device, such as a printer or a display device. The microprocessor includes logic circuitry for generating a Valid Memory Address (VMA) output. The VMA output is used to generate an enable signal applied to the memory and the adaptor to enable the memory and the adaptor to be accessed by the microprocessor when the binary address on the address bus is valid and to prevent the memory and the adaptor from being accessed by the microprocessor when the binary address on the address bus is not valid with respect to the microprocessor.

Valid memory address enable system for a microprocessor system

A microprocessor system includes a microprocessor, a memory, and an interface adaptor all coupled to a data bus. The interface adaptor is coupled between the data bus and a peripheral device, such as a teleprinter. A first interrupt conductor is connected to the peripheral device and to interrupt logic circuitry in the interface adaptor. A second interrupt conductor is connected to the microprocessor and the interrupt logic circuitry. The interrupt logic circuitry is also coupled to and interrogatable by the microprocessor via the data bus. The interrupt logic circuitry stores interrupt contrl information from the data bus, and generates a second interrupt signal on the second interrupt conductor in response to the stored interrupt control information and an interrupt signal generated on the first interrupt conductor by the peripheral device. The interrupt logic circuitry also stores status information indicative of the occurrence of the first interrupt signal and effects interrogation of that status via the data bus.

Interrupt system for microprocessor system

A digital system comprises a plurality of metal-oxide-semiconductors (MOS) chip random access memory (RAM) and read only memory (ROM) and peripheral interface adaptor circuits used as part of the computer coupled to a common bidirectional data bus which is coupled to and controlled by a microprocessor unit (MPU) chip. In the digital system, data transfers on the common bidirectional data bus are accomplished without the use of a memory synchronization signal so that a special signal conductor indicating when the memory is ready to transfer data is not required. This is accomplished by logic circuitry which expands a clock signal pulse which is applied to the microprocessor chip whenever a memory location is addressed which has a longer access time than is consistent with the width of the pulse ordinarily applied to the microprocessor to effect its operation.

Pulse expanding system for microprocessor systems with slow memory

A microprocessor includes a data bus and an address bus. The address bus has first and second sections coupled together in series by bus switch circuitry. The microprocessor also includes control circuitry for controlling various data transfers in the microprocessor. The bus switch circuitry includes a plurality of MOSFETs each having their gate electrodes coupled to the control circuitry and having their sources and drains coupled to corresponding bus conductors of the first and second sections of the address bus. A program counter, incrementer and other working registers are coupled between the address bus first section and the data bus. An accumulator register and an arithmetic logic unit are coupled between the second section of address bus and the data bus. An index register for storing information to be utilized in an indexed addressing mode of operation is coupled to both the first and second sections of the address bus and to the data bus.

Microprocessor having index register coupled to serial-coupled address

Interrupt circuitry is provided for an MOS integrated circuit microprocessor chip. An input of the microprocessor chip is adapted to having an external interrupt signal applied thereto for interrupting the operation of the microprocessor chip within a digital data processing system. The input is coupled to circuitry which inhibits loading of the next instruction to be executed in response to an interrupt request signal applied to the interrupt request input, and also forces a code into the instruction register in response to the interrupt request signal. The code is substantially similar to the code for a software wait instruction or a software interrupt instruction. Therefore, much of the same circuitry within the microprocessor can be used for executing an interrupt operation, a software wait instruction, or a software interrupt instruction.

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Scottsdale, AZ, United States of America

Thomas H Bennett