Rf Micro Devices, Inc.

Globalfoundries Inc.

Mstar Semiconductor, Inc.

Globalfoundries U.S. Inc.

Thomas Gregory Mckay

Michael Carroll

Stephen Allott

Daniel Charles Kerr

Joseph M Gering

Jonathan Gowing

Marcus Granger-Jones

Julio C Costa

Cyril Valadon

Robert Seidel

Christian Rye Iversen

Arul Balasubramaniyan

Tibor Bolom

Tony Ivanov

Konstantinos Manetakis

Qiao Yang

An amplifier includes an input transistor pair connected to amplifier input nodes, a complementary transistor pair connected to a common bias, amplifier output nodes connected to the input transistor pair and the complementary transistor pair, and variable capacitors connected between the complementary transistor pair and the amplifier output nodes.

Adjustable capacitors to improve linearity of low noise amplifier

Methods form amplifier device structures that include first-third amplifier devices. The first amplifier device produces an intermediate signal. The second amplifier device is connected to an input of the first amplifier device and produces an amplified inverted output signal. The third amplifier device inverts the intermediate signal to produce an amplified non-inverted output signal that is complementary to the amplified inverted output signal. A resistor feedback loop is connected to the input and output of the first amplifier device. A gain ratio of the gain of the third amplifier device to the gain of the second amplifier device matches a resistance ratio of the source resistance of the input signal to the resistance of the resistor added to the source resistance. Also, DC loop circuits are connected to the first-third amplifier devices, and each of the DC loop circuits connects an amplifier device output to an amplifier device input.

Wideband low noise amplifier having DC loops with back gate biased transistors

Disclosed are integrated circuit (IC) structure embodiments with a three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) in back-end-of-the-line (BEOL) metal levels. The MIMCAP includes a plurality of high aspect ratio trenches that extend through at least one relatively thick dielectric layer within the metal levels. Conformal layers of a metal, an insulator and another metal line the trenches and cover the top of the dielectric layer in the area of the MIMCAP. Different configurations for the bottom and top electrode contacts can be used including, for example, one configuration where the top electrode contact is a dual-damascene structure within an ultra-thick metal (UTM) level above the MIMCAP and another configuration where both the top and bottom electrode contacts are such dual-damascene structures. Also disclosed are method embodiments for forming IC structures with such a MIMCAP and these method embodiments can be readily integrated into current BEOL processing, including UTM-level dual-damascene processing.

Three-dimensional (3D) metal-insulator-metal capacitor (MIMCAP) and method

Embodiments of the present disclosure provide a circuit structure and method for power amplifier control with forward and reverse voltage biases to transistor back-gate regions. A circuit structure according to the disclosure can include: a power amplifier (PA) circuit having first and second transistors, the first and second transistors each including a back-gate region, wherein the back-gate region of each of the first and second transistors is positioned within a doped substrate separated from a semiconductor region by a buried insulator layer; and an analog voltage source coupled to the back-gate regions of the first and second transistors of the PA circuit, such that the analog voltage source alternatively supplies a forward bias voltage or a reverse bias voltage to the back-gate regions of the first and second transistors of the PA circuit to produce a continuously sloped power ramping profile.

Power amplifier ramping and power control with forward and reverse back-gate bias

Comparators include (among other components) two inputs, an output, and two pairs of transistors (each connected to a different one of the inputs). Both pairs of transistors are connected to the output. Additionally, a first signal generator is connected to the first transistor in each of the pairs of transistors, and a second signal generator is connected to the second transistor in each of the pairs of transistors. The first signal generator and the second signal generator output on/off control signals that have timing patterns that are inverted relative to one another, and this causes only the first transistor or the second transistor in each of the pairs of transistors to be active at any given time. Thus, the single active transistor in the first pair of transistors and the single active transistor in the second pair of transistors amplify the difference between the two inputs, through the output.

Comparator having duplicate alternately used transistors

At least one method, apparatus and system disclosed involves providing semiconductor device having transistors comprising back gates and front gates. The semiconductor device comprises a signal processing unit for processing an input signal to provide an output signal. The signal processing unit includes a first transistor and a second transistor. The first transistor includes a first back gate electrically coupled to a first front gate. The signal processing unit also includes a second transistor operatively coupled to the first transistor. The second transistor includes a second back gate electrically coupled to a second front gate. The semiconductor device also includes a gain circuit for providing a gain upon the output signal. The semiconductor device also includes a bias circuit to provide a first bias signal to the first back gate and a second bias signal to the second back gate.

Method, apparatus and system for back gate biasing for FD-SOI devices

One aspect of the present invention includes a radio frequency (RF) receiver having a first mixer and a second mixer. The first mixer may be an I-mixer and the second mixer a Q-mixer for downconverting the received RF signal. An impedance circuit is disposed between the first mixer and the second mixer to decouple the channels. In another aspect of present invention, the RF receiver includes a digital filter having at least one complex coefficient. The digital filter exhibits asymmetrical frequency response, and may be used to compensate the asymmetrical frequency response of another filter in the RF receiver.

Multimode receiver with complex filter

One aspect of the present invention includes an RF including a first mixer receiving an RF signal. A second mixer also receivers the RF signal. A resonant circuit couples to a common input of the first mixer and the second mixer. A second polyphase reactive circuit coupled to an output of the second mixer. In one embodiment, a direct current circuit coupled to the output of the first mixer, injecting direct current into the system. The resonant circuit is set at a resonance frequency such that a voltage across the second polyphase reactive circuit is a predetermined voltage.

RF receiver with sideband symmetry circuit

Embodiments of a radio frequency (RF) circuit provide translational filtering in accordance with an input impedance response that is an impedance image of a reactive circuit impedance response from a poly phase reactive circuit. The RF circuit may include a first mixer circuit that provides a first frequency offset for the impedance image and a second mixer circuit that provides an additional frequency offset. Accordingly, the second mixer circuit may allow for adjustments to a total frequency offset of the impedance image. The second mixer circuit may also be configured so that the impedance image rejects a negative frequency impedance response of the reactive circuit impedance response.

Discrete time polyphase mixer

A non-overlapping clock generator including an enabling module and N pulse-generating modules connected as a ring is provided. When the ith input node has a high voltage level, the enabling module enables the ith pulse-generating module so as to trigger the ith pulse-generating module to discharge the ith input node. After the ith input node has been discharged to a low voltage level, the ith pulse-generating module charges the ith output node to the high voltage level.

Non-overlapping clock generator

Embodiments of a radio frequency (RF) circuit provide translational filtering in accordance with an input impedance response that is an impedance image of a reactive circuit impedance response from a polyphase reactive circuit. The RF circuit may include a first mixer circuit that provides a first frequency offset for the impedance image and a second mixer circuit that provides an additional frequency offset. Accordingly, the second mixer circuit may allow for adjustments to a total frequency offset of the impedance image. The second mixer circuit may also be configured so that the impedance image rejects a negative frequency impedance response of the reactive circuit impedance response.

The present invention is a controllable input impedance RF mixer, which when fed from a high impedance source, such as a current source, provides a high quality factor (Q) impedance response associated with an impedance peak. The high-Q impedance response may be used as a high-Q RF bandpass filter in a receive path upstream of down conversion, which may improve receiver selectivity and replace surface acoustic wave (SAW) or other RF filters. The present invention uses polyphase reactive circuitry, such as capacitive elements, coupled to the down conversion outputs of an RF mixer. The RF mixer mixes RF input signals with local oscillator signals to translate the impedance of the polyphase reactive circuitry into the RF input impedance of the RF mixer. The RF input impedance includes at least one impedance peak. The local oscillator signals are non-overlapping to maximize the energy transferred to the polyphase reactive circuitry.

Controllable input impedance radio frequency mixer

The present invention relates to using a trap-rich layer, such as a polycrystalline Silicon layer, over a semiconductor substrate to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate at radio frequency (RF) frequencies. The trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.

Linearity improvements of semiconductor substrate based radio frequency devices

The present invention relates to using a potentially trap-rich layer, such as a polycrystalline Silicon layer, over a passivation region of a semiconductor substrate or a Silicon-on-insulator (SOI) device layer to substantially immobilize a surface conduction layer at the surface of the semiconductor substrate or SOI device layer at radio frequency (RF) frequencies. The potentially trap-rich layer may have a high density of traps that trap carriers from the surface conduction layer. The average release time from the traps may be longer than the period of any present RF signals, thereby effectively immobilizing the surface conduction layer, which may substantially prevent capacitance and inductance changes due to the RF signals. Therefore, harmonic distortion of the RF signals may be significantly reduced or eliminated. The semiconductor substrate may be a Silicon substrate, a Gallium Arsenide substrate, or another substrate.

Growing community of inventors

Boulder Creek, CA, United States of America

Thomas Gregory Mckay