Biosig Technologies, Inc.

Mayo Foundation for Medical Education and Research

Light-Based Technologies Incorporated

Koninklijke Philips Corporation N.v.

Thomas George Foxall

Budimir S Drakulic

Sina Fakhar

Branislav Vlajinic

Samuel J Asirvatham

Gregory Bernard Sheehan

Miroslaw Marek Grotkowski

Tom William Thornton

Milen Moussakov

Stephen Christian Wilson

Brent York

Described herein are embodiments of a switching network for integrating electrophysiology components into an electrophysiology system. These electrophysiology components may include electrophysiology recorder, three-dimensional mapping systems, radio frequency generators, and stimulators. The switching network provides switchable connections, which allow the electrophysiology system to be reconfigured to perform different electrophysiology procedures, such as heart signal recording and mapping, cardiac ablation, or cardiac pacing. A recorder may provide control signals to the switching network to change connections between electrophysiology equipment and a catheter in a patient's heart. The electrophysiology system may control generation of biphasic pulses for use in cardiac pacing. The electrophysiology system may reconfigure the effective size the tip electrode of a split tip catheter.

Controlled switching network for electrophysiology procedures

Systems, methods, and computer program product embodiments are disclosed for displaying cardiac signals based on a signal pattern. An embodiment operates by accessing an input cardiac signal. The embodiment matches a portion of the input cardiac signal to a known signal pattern. The embodiment then displays an indication of a degree of the match.

Systems and methods to display cardiac signals based on a signal pattern

Systems, methods, and computer program product embodiments are disclosed for removing any fixed frequency interfering signal from an input signal without introducing artifacts that are not part of the original signal of interest. An embodiment operates by using a virtual buffer with a length that matches a length of one cycle of an interfering signal. The embodiment extracts the interfering signal into the virtual buffer. For a sample in the next cycle of the interfering signal that corresponds to a virtual memory location for the virtual buffer, the embodiment can update one or more physical memory locations of the virtual buffer that are in the vicinity of the virtual memory location. This use of virtual buffer can remove any interfering signal without creating the artifacts associated with conventional notch filters.

Universal notch filter

Systems, methods, and computer program product embodiments are disclosed for performing electrophysiology (EP) signal processing. An embodiment includes an electrocardiogram (ECG) circuit board configured to process an ECG signal. The embodiment further includes a plurality of intracardiac (IC) circuit boards, each configured to process a corresponding IC signal. The ECG circuit board and the plurality of IC circuit boards share substantially a same circuit configuration and components. The ECG circuit board further processes the ECG signal using substantially a same path as each IC circuit board uses to process its corresponding IC signal.

Systems and methods for performing electrophysiology (EP) signal processing

Apparatus and methods remove a voltage offset from an electrical signal, specifically a biomedical signal. A signal is received at a first operational amplifier and is amplified by a gain. An amplitude of the signal is monitored, by a first pair of diode stages coupled to an output of the first operational amplifier, for the voltage offset. The amplitude of the signal is then attenuated by the first pair of diode stages and a plurality of timing banks. The attenuating includes limiting charging, by the first pair of diode stages, of the plurality of timing banks and setting a time constant based on the charging. The attenuating removes the voltage offset persisting at a threshold for a duration of at least the time constant. Saturation of the signal is limited to a saturation recovery time while the saturated signal is gradually pulled into monitoring range over the saturation recovery time.

Apparatus and methods for removing a large-signal voltage offset from a biomedical signal

Apparatus for processing biomedical signals for display

Systems, methods, and computer program product embodiments are disclosed for filtering noise from an input signal. An embodiment accesses the input signal having a first harmonic frequency and having the noise. The embodiment determines a quiet period in the input signal. The embodiment stores samples of the noise of the input signal in a buffer during the quiet period. The embodiment subtracts the samples from a single cycle of the noise in the buffer from the input signal to create a filtered signal. The embodiment then repeats the determining, storing, and subtracting to refine the filtered signal.

Systems, apparatus, and methods are disclosed for processing biomedical signals. An electrophysiology (EP) system includes a differential circuit to process the biomedical signals; a differential amplifier circuit to amplify an output of the differential circuit; an analog-to-digital converter to digitize an output of the differential amplifier circuit; a communication module to interface between the analog-to-digital converter and a digital processing stage having a plurality of signal modules; and at least one processor to execute the plurality of signal modules, applying digital signal processing to the output from the analog-to-digital converter, to extract features of interest of the biomedical signals.

Systems and methods for signal acquisition and visualization

Systems, methods, and computer program product embodiments are disclosed for processing and displaying multiple signals in near real-time. An embodiment operates by processing, using a first digital signal processor (DSP) of a first signal module, a first packet associated with a first signal. The embodiment also processes, using a second DSP of a second signal module, a second packet associated with a second signal. The embodiment equalizes a first processing delay associated with the first DSP with a second processing delay associated with the second DSP such that the first DSP completes processing of the first packet approximately simultaneously with the second DSP completing processing of the second packet. The embodiment then displays the processed first packet approximately simultaneously with the display of the processed second packet.

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Surrey, Canada

Thomas George Foxall