Intel Corporation

Thomas Gaertner

Naveen Neelakantam

Niranjan L Cooray

Keith D Underwood

Fernando Latorre

Pedro Lopez

Jaroslaw Topp

Varun Mohandru

Li-Gao Zei

Rami May

Norbert Foerster

A processor includes a processor core including an execution unit to execute instructions, and a cache memory. The cache memory includes a controller to update each of a plurality of stale indicators in response to a lazy flush instruction. Each stale indicator is associated with respective data, and each updated stale indicator is to indicate that the respective data is stale. The cache memory also includes a plurality of cache lines. Each cache line is to store corresponding data and a foreground tag that includes a respective virtual address associated with the corresponding data, and that includes the associated stale indicator. Other embodiments are described as claimed.

Method and apparatus to implement lazy flush in a virtually tagged cache memory

An embodiment may include circuitry to determine, at least in part, at least one first output to which to route at least one packet, based, at least in part upon, a first output determination and a second output determination. The first output determination may select at least one second output based at least in part upon at least one deterministic output selection algorithm. The second output determination may select at least one third output based at least in part upon at least one pseudo-random output selection algorithm. The at least one pseudo-random output selection algorithm may be based, at least in part, upon a counter value. Many modifications, variations, and alternatives are possible without departing from this embodiment.

Packet routing

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Braunschweig, Germany

Thomas Gaertner