Marvell International Limited

Marvellworld Trade Ltd.

Thomas G Warner

William B Weiser

In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with the memory device via a bus, such as a data control system, system bus, or memory bus. Memory maintains values, such as a control register maintaining control register values, which are adjustable to tune bus timing margins in multi-dimensions. The bus timing margins are tunable for implementation of a memory device controller with one or more of the memory devices. A memory timing tuner is implemented to adjust the values to tune the bus timing margins in the multi-dimensions.

Multi-dimension memory timing tuner

The present disclosure describes techniques for scalable embedded memory programming. In some aspects data is received at a first communication interface from a host device, at least a portion of the data is stored to a memory device supported by a printed circuit board, and the data is transmitted to a target device via a second communication interface.

Programming target devices via traces that traverse a structurally compromised region of a printed circuit board (PCB)

In embodiments of a multi-dimension memory timing tuner, a memory device controller that can be interfaced with one or more memory devices is coupled to a memory device for data communication with the memory device via a memory bus. Control registers maintain control register values that are adjustable to tune memory bus timing margins in multi-dimensions. The memory bus timing margins are tunable for implementation of a memory device controller with one or more of the memory devices. A memory timing tuner is implemented to adjust the control register values to tune the memory bus timing margins in the multi-dimensions.

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Boise, ID, United States of America

Thomas G Warner