Samsung Electronics Co., Ltd.

Array Microsystems, Inc.

Thomas G Kopet

Stephen D Lew

Gerry C Lui Kuo

Bradford G Taylor

Gerry C Luikuo

The present invention provides an image compression/decompression coprocessor which is integrated on a single chip. The control bus has a control unit which is connected by an internal, global bus to a number of different, special purpose processing units. Each of the processing units is specifically designed to handle only certain steps in compression and decompression processes.

Image compression coprocessor with data flow control and multiple

A motion estimation coprocessor for use in a video data system. The motion estimation coprocessor may be used with a video memory that subdivides a P row.times.Q column image of pixels into several pages. The page structure enables efficient loading of video data into the coprocessor. The motion estimation coprocessor may perform several block matches simultaneously. The motion estimation coprocessor may perform exhaustive block matching or use a hierarchical search.

Motion estimation coprocessor

A video interface unit for transferring image data between video memory and video processing components interfaces with a video bus. The video interface unit has a partionable data buffer. The partionable buffer enables data to be accessed without redundant fetches of image data and for associated processing of data to be interleaved.

Growing community of inventors

Colorado Springs, CO, United States of America

Thomas G Kopet