International Business Machines Corporation

Thomas Fuchs

Joerg-Stephan Vogt

Christian Jacobi

Anthony Thomas Sofia

Reiner Rieke

Maarten Jakob Boersma

David Lang

Peter Bergersen Yocom

Markus Kaltenbach

Norbert Hagspiel

Frank Haverkamp

Hartmut Droege

Jörg-Stephan Vogt

Gunnar Von Boehn

Michael Ruettger

Chung-Lung K Shum

Ulrich Mayer

Scott Barnett Swaney

Thomas G Koehler

Friedrich Schroeder

Thomas St Pierre

A sort device includes a compare unit on one level of a hierarchical structure that includes a plurality of levels. The compare unit to compare one beat of one record with another beat of another record to provide a winner beat. The sort device further includes another compare unit on another level of the hierarchical structure to provide a further beat to the compare unit, and a request pipe to be used to request that the other compare unit provide the further beat to the compare unit.

Hierarchical sort/merge structure using a request pipe

Multi-cycle key compare units. A compare unit includes a comparator, additional compare logic and at least one pair of buffers which provide input to the comparator. The compare unit sorts variable length records in streaming mode without the need for complex state machines to maintain state relating to the comparing. A record may have a variable length key and optional variable length data. The record and/or the key is split into fixed, pre-defined lengths. The total key and record lengths are unknown to the comparator of the compare unit.

Multi-cycle key compares for keys and records of variable length

A list of input registers and output registers for a circuit design are provided. The circuit design is modified by traversing output connections paths for each input register and replacing any register in the output connection paths with a wire unless the register is a listed output register. An initial total cycle time value for the modified circuit design is determined. A gate level description for the modified circuit design is obtained by a macro synthesis with the initial total cycle time value. The total cycle time value for the modified circuit design is then varied in order to determine the theoretical limit of the modified circuit design. This theoretical limit is realized when negative slacks are present in a macro synthesis of the modified circuit design for a given total cycle time value. Based on this theoretical limit, the minimum pipeline depth of the circuit design is determined.

Pipeline depth exploration in a register transfer level design description of an electronic circuit

An output sequence of data elements is processed. The output sequence of data elements represents a sequence of input data elements in a compressed format. An output data element includes a backward reference for each string in the input data elements that occurs again in an input data element that is used to produce the output data element. A backward reference identified in a selected output data element is used for selecting the string to which it refers in the stored input data elements. The selected string is combined with strings of one or more subsequent output data elements. A matching sequence in the stored input data elements matching at least part of one or more combined strings is found. A combined string of the one or more combined strings having the longest matching sequence is selected. The backward reference is redefined to indicate the longest matching sequence.

Compression ratio for a compression engine

Concurrently writing an uncompressed data element, if the uncompressed data element comprises an indication that it is valid, in a main hash table using a first address generated by a first hash function, and reading a first data element from the main hash table using the first address. Introducing a first pipeline delay for maintaining the uncompressed data element in a first data path until the first data element is read. Concurrently writing the first data element to a victim hash table, if the first data element comprises an indication that it is valid, using a second address generated by a second hash function, and reading a second data element from the victim hash table using a third address generated by the second hash function. Introducing a second pipeline delay for maintaining the uncompressed data element in the first data path until the second data element is read.

Hardware compression to find backward references with multi-level hashes

A hardware circuit for returning single precision denormal results to double precision. A hardware circuit component configured to count leading zeros of an unrounded single precision denormal result. A hardware circuit component configured to pre-compute a first exponent and a second exponent for the unrounded single precision denormal result. A hardware circuit component configured to perform a second normalization of the rounded single precision denormal result back to architected format.

Fast normalization in a mixed precision floating-point unit

An output sequence of data elements is processed. The output sequence of data elements represents a sequence of input data elements in a compressed format. An output data element comprises a backward reference for each string in the input data elements that occurs again in an input data element that is used to produce the output data element. A backward reference identified in a selected output data element is used for selecting the string to which it refers in the stored input data elements. The selected string is combined with strings of one or more subsequent output data elements. A matching sequence in the stored input data elements matching at least part of one or more combined strings is found. A combined string of the one or more combined strings having the longest matching sequence is selected. The backward reference is redefined to indicate the longest matching sequence.

Embodiments relate to providing a data stream interface for offloading the inflation/deflation processing of data to a stateless compression accelerator. An aspect includes transmitting a request to inflate or deflate a data stream to a compression accelerator. The request may include references to an input buffer for storing input data from the data stream, an output buffer for storing processed input data, and a state data control block for storing a stream state. The stream state is provided to the compression accelerator to continue processing the data stream responsive to the request being a subsequent request. The compression accelerator is instructed to store a current stream state in the state data control block responsive to the request being a non-final request. Accordingly, the current stream state is received from the compression accelerator responsive to the request being a non-final request. The processed input data is received from the compression accelerator.

Compression/decompression accelerator protocol for software/hardware integration

A multiprocessor electronic circuit and an electronic data processing system comprising such circuit are disclosed for reducing the power consumption and the chip area consumption of a multiprocessor system having cryptographic functionality. In one embodiment, the multiprocessor electronic circuit comprises a plurality of processors, a single cryptographic processing unit that comprises a plurality of input/output buffer pairs and two cryptographic engines, a cipher engine and a hash engine, and associated control logic.

Growing community of inventors

Bietigheim-Bissingen, Germany

Thomas Fuchs