Melexis Technologies Nv

Melexis Nv

Melexis Bulgaria Ltd

Thomas Freitag

Michael Frey

Christian Paintz

Michael Bender

Jörgen Sturm

Andreas Ott

Heiko Grimm

Benoit Heroux

Philippe Laugier

Gunnar Munder

Raik Frost

Anton Babushkin

Enrico Reinhardt

Detlef Klose

Martin Bölter

Andrea Baschirotto

Eric Sachse

Jian Chen

Dirk Leman

Xing Zuo

Joergen Sturm

Francois Piette

Viktor Petri

Sandro Purfuerst

Heiko Leutert

Axel Fanget

Cliff De Locht

Andreas Laute

Sebastian Spiegler

Nicolas Vielcanet

Jan Heynlein

Veit Zöppig

Tom Ströhla

Torsten Bacher

Philip Mckenna

Federico D'Aniello

Jens Röpcke

Federico D'ANIELLO

Sandro PURFÜRST

A method for autoconfiguration of a plurality of nodes in a linear network allows extracting the address and position of each node. The nodes are identified by a unique identifier. The method comprises choosing a node in a network and extracting its identifier, and for the first node to the last but one node, transmitting a current in the network from the chosen node, and reading the direction of the current flowing through at least the nodes not chosen in previous iteration cycles. The identifier is linked with the direction of the current for said not chosen nodes, obtaining the position of said not chosen nodes relative to the chosen node. These steps are repeated by choosing a different node not chosen before. Autoconfiguration is finished when the identifier of each node is extracted, and the physical position of each node is determined.

Method of autoconfiguration of communication network

A safety related light system includes: one light source, a first control circuit, and a second control circuit. One of the first control circuit or the second control circuit is selectively enabled to operate in a drive mode to operate the one light source.

Light system

A system for characterizing a transistor circuit which has a local minimum in its transfer characteristic by finding its local minimum. The system comprises: a bias voltage generator for generating a toggling signal; a multiplier configured for multiplying an electrical signal which is a function of the drain source current of the transistor circuit, with a waveform alternating between two predefined values synchronously with the toggling signal; a first integrator configured for integrating the electrical signal from the multiplier, and wherein if more integrators are present, linear combinations of output signals of the integrators are provided to the further integrators; a summator configured for summing the toggling signal and an integration signal and configured for outputting the sum to the gate of the transistor circuit.

System for characterizing a transistor circuit

A transmitter device is provided for transmission of data via DC power distribution lines includes a sequence generator arranged for receiving a raw data bit stream to be transmitted over a positive and a negative DC power distribution line and for deriving a switching sequence based on the raw data bit stream, and a circuit including one or more capacitors and a plurality of switches controllable with the switching sequence derived in the sequence generator.

Transmitter for power line communication

A method for communicating between a master and a plurality of slaves includes generating a communication frame including generating a slave data frame in each slave. The slave data frame has a data packet including one or more data bytes and at least one gap of variable time length comprising no information in the slave data frame. The gap may be at the beginning of said slave data frame before the beginning of the first data byte of said data packet and/or at the end of said data packet after the end of a last data byte of said data packet, where the gaps have a time length dependency based on parameters locally stored in each of said at least one slave. The slave data frame is transmitted sequentially where the gap increases for each subsequent slave.

High speed communication system

A memory device includes a non-volatile memory block, a protection unit arranged for connecting to a communication bus, and a sequencer arranged to receive commands from the protection unit. A logic circuit is arranged to output an enabling signal, and includes first and second logic subcircuits, and a combiner logic circuit.

Memory device

The present invention relates to a receiver circuit for processing an incoming bit stream from a bus system. The circuit comprises an analog interface for converting the analog signal to a digital input data stream. The interface comprises an analog filter and a switch to process the analog signal before generating the digital input data stream using the filter if, and only if, a selection criterion controlling the switch is met. The circuit comprises a frame decoding unit for decoding a data frame encoded in the digital input data stream in accordance with a CAN protocol, and a frame processing unit that comprises a flexible data rate detector and a recessive bit counter for counting consecutive recessive bits after detecting the flexible data rate frame. The selection criterion is satisfied when the flexible data rate frame is detected and unsatisfied when the recessive bit counter reaches a predetermined number.

Flexible data rate handling in data bus receiver

An edge crack monitoring system for an integrated circuit provided on a die, comprises a conductive trace comprising at least a first conductive path for allowing current in a first direction, and a second adjacent conductive path for allowing current in a second direction opposite to the first direction. Both adjacent conductive paths form at least one loop surrounding a semiconductor device on a die. The arrangement of the trace is adapted to provide compensation of EM interferences. The trace comprises two terminals being connectable to a detection circuit for detecting damages by generating a fault signal upon detection of disruption of the conductive trace due to a damage. The conductive trace comprises high resistance portions with a resistance of at least 1 k&#x3a9;, adapted for reducing self-resonance.

Die edge integrity monitoring system

A brushless DC motor driver for driving a brushless DC motor which comprises at least one coil wherein the control unit is adapted for applying a PWM driving signal to the at least one coil of the brushless DC motor such that a current through the at least one coil is always bigger than a pre-defined undercurrent limit.

Driver and method for low inductance motor

A system having a plurality of devices configured in a daisy chain network including a communication bus connecting the devices and adapted to exchange address-setting information. Each device includes an input pin adapted to receive via an input signal line different from the communication bus a signal comprising configuration information for configuring at least the device; a configuration handling unit adapted to detect a configuration mode and to configure the device according to the configuration information; an indicator adapted to indicate whether the configuration handling unit has finished configuring the device; an output pin adapted to forward the configuration information to the daisy chain network when the indicator indicates the configuration of the device is done; and a safety handling unit adapted to be operable in a safety handling mode when the indicator indicates the configuration of the device is done.

Device for use in a configurable network

The present invention relates to an integrated circuit device for controlling LIN slave nodes based on a control signal transmitted by a LIN master control device. The IC device comprises a slave node circuit for processing the control signal when received in the form of a LIN message frame via a first data line terminal. The IC device also comprises a master node circuit for processing further control signals to be transmitted in the form of LIN message frames via a second data line terminal to the LIN slave nodes. The IC device also comprises a processing unit for controlling the LIN slave nodes based on the control signal by composing the further control signals.

Local interconnect network bus architecture

A transmitter for establishing communication between a device and a differential network bus includes current driving means connected to each of the two conduction lines of the differential network bus, through a first and second conduction paths of the transmitter; at least one unidirectional current regulator for extracting a first current equal to a known ratio of a parasitic current circulating through the first conduction path, with a direction inverse to the driving current through the conduction path connected to one of the lines of the differential bus; means for obtaining, from the first current, a second current with a magnitude equal to the original magnitude of the parasitic current; and means for introducing the second current into the second conduction path connected to the other line of the differential bus.

Transceiver unit for transmitting data via a differential bus

A device for supervising ports of an integrated circuit is arranged for exchanging information with a central processing unit of an integrated circuit and for communicating with ports of the integrated circuit. The device comprises address decoding means, access control means, and parity controlling means. The device for supervising ports comprises read-back information means arranged for receiving input from the port and for passing that input to the parity control means and in that the address decoding means, the access control means, the read-back information means and the parity controlling means are arranged to be operative in a background loop wherein a range of port addresses is monitored. The read-back information means reads data and one or more parity bits stored on ports with an address in the range and the parity controlling means performs a parity check on the one or more parity bits stored on the ports.

Device for supervising and initializing ports

A data transceiver device for bus communication includes: first and second semiconductor areas; a galvanic isolation means to galvanically isolate the first and second semiconductor areas; an input for receiving a signal to be transferred from the first semiconductor area to the second semiconductor area; a first capacitor in a first signal path and a second capacitor in a second signal path, each capacitor having a first plate connected to the first semiconductor area and a second plate connected to the second semiconductor area and each arranged for transferring a version of the received signal via the first and second signal paths, respectively; storage means having memory states controllable by the versions of the received signal and arranged to derive from the versions of the received signal the memory states. The storage means is arranged to obtain from the memory states an output signal in according to the received signal.

Transceiver with galvanic isolation means

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Plaue, Germany

Thomas Freitag